Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40929 )
Change subject: arch-power: Refactor rotate instructions
......................................................................
arch-power: Refactor rotate instructions
This renames the mask span fields and the rotate helper
of the base class.
Change-Id: I120006a0c052fcc34eb154a68d4b7f70a464df65
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
4 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index fc42911..d921b5d 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -729,7 +729,7 @@
}
// Print the shift, mask begin and mask end
- ss << ", " << sh << ", " << mb << ", " << me;
+ ss << ", " << sh << ", " << maskBeg << ", " << maskEnd;
return ss.str();
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index aab6910..d969362 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -643,31 +643,33 @@
/**
- * Class for integer rotate operations.
+ * Class for integer rotate operations with a shift amount obtained
+ * from a register or an immediate and the first and last bits of a
+ * mask obtained from immediates.
*/
class IntRotateOp : public IntShiftOp
{
protected:
- uint32_t mb;
- uint32_t me;
uint32_t fullMask;
+ uint32_t maskBeg;
+ uint32_t maskEnd;
/// Constructor
IntRotateOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: IntShiftOp(mnem, _machInst, __opClass),
- mb(machInst.mb),
- me(machInst.me)
+ maskBeg(machInst.mb),
+ maskEnd(machInst.me)
{
- if (me >= mb) {
- fullMask = mask(31 - mb, 31 - me);
+ if (maskEnd >= maskBeg) {
+ fullMask = mask(31 - maskBeg, 31 - maskEnd);
} else {
- fullMask = ~mask(31 - (me + 1), 31 - (mb - 1));
+ fullMask = ~mask(31 - (maskEnd + 1), 31 - (maskBeg - 1));
}
}
- uint32_t
- rotateValue(uint32_t rs, uint32_t shift) const
+ inline uint32_t
+ rotate(uint32_t rs, uint32_t sh) const
{
uint32_t n = shift & 31;
return (rs << n) | (rs >> (32 - n));
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e997699..ef66ac9 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -266,9 +266,9 @@
}
format IntRotateOp {
- 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
- 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
- 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) |
+ 21: rlwinm({{ Ra = rotate(Rs, sh) & fullMask; }});
+ 23: rlwnm({{ Ra = rotate(Rs, Rb) & fullMask; }});
+ 20: rlwimi({{ Ra = (rotate(Rs, sh) & fullMask) |
(Ra & ~fullMask); }});
}
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 571a1b6..bc52340 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -526,15 +526,17 @@
}};
-// A special format for rotate instructions which use certain fields
-// from the instruction's binary encoding. We need two versions for each
-// instruction to deal with the Rc bit.
+// Integer instructions with or without immediate that perform rotate
+// operations. All instructions write to Ra and use Rs as a source
+// register. If immediate is not used, Rb is also used as a source
+// register. We need two versions for each instruction to deal with
+// the Rc bit.
def format IntRotateOp(code, inst_flags = []) {{
# The result is always in Ra
dict = {'result':'Ra'}
- # Setup the code for when Rc is set
+ # Code when Rc is set
code_rc1 = readXERCode + code + computeCR0Code % dict
# Generate the first class
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I120006a0c052fcc34eb154a68d4b7f70a464df65
Gerrit-Change-Number: 40929
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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