Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40931 )
Change subject: arch-power: Fix disassembly for rotate instructions
......................................................................
arch-power: Fix disassembly for rotate instructions
This fixes disassembly generated for integer rotate
instructions based on special use cases for which the
Power ISA provides extended mnemonics.
Change-Id: I8c33e7c8128ad62d856ce050df8a91b2dfd52f4c
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/integer.cc
1 file changed, 65 insertions(+), 3 deletions(-)
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index d921b5d..aaa7925 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -712,8 +712,40 @@
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+ bool printSecondSrc = true;
+ bool printShift = true;
+ bool printMaskBeg = true;
+ bool printMaskEnd = true;
- ccprintf(ss, "%-10s ", mnemonic);
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (!myMnemonic.compare("rlwinm")) {
+ if (maskBeg == 0 && maskEnd == 31) {
+ myMnemonic = "rotlwi";
+ printMaskBeg = false;
+ printMaskEnd = false;
+ } else if (shift == 0 && maskEnd == 31) {
+ myMnemonic = "clrlwi";
+ printShift = false;
+ printMaskEnd = false;
+ }
+ printSecondSrc = false;
+ } else if (!myMnemonic.compare("rlwnm")) {
+ if (maskBeg == 0 && maskEnd == 31) {
+ myMnemonic = "rotlw";
+ printMaskBeg = false;
+ printMaskEnd = false;
+ }
+ printShift = false;
+ } else if (!myMnemonic.compare("rlwimi")) {
+ printSecondSrc = false;
+ }
+
+ // Additional characters depending on isa bits being set
+ if (rcSet) myMnemonic = myMnemonic + ".";
+ ccprintf(ss, "%-10s ", myMnemonic);
// Print the first destination only
if (_numDestRegs > 0) {
@@ -726,10 +758,40 @@
ss << ", ";
}
printReg(ss, srcRegIdx(0));
+
+ // Print the second source register
+ if (printSecondSrc) {
+
+ // If the instruction updates the CR, the destination register
+ // Ra is read and thus, it becomes the second source register
+ // due to its higher precedence over Rb. In this case, it must
+ // be skipped.
+ if (rcSet) {
+ if (_numSrcRegs > 2) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(2));
+ }
+ } else {
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
+ }
+ }
}
- // Print the shift, mask begin and mask end
- ss << ", " << sh << ", " << maskBeg << ", " << maskEnd;
+ // Print the shift value
+ if (printShift) {
+ ss << ", " << shift;
+ }
+
+ // Print the mask bounds
+ if (printMaskBeg) {
+ ss << ", " << maskBeg;
+ }
+ if (printMaskEnd) {
+ ss << ", " << maskEnd;
+ }
return ss.str();
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8c33e7c8128ad62d856ce050df8a91b2dfd52f4c
Gerrit-Change-Number: 40931
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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