Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41317 )
Change subject: mem: XBar drawing mem_side ranges with MemMap Dflag
......................................................................
mem: XBar drawing mem_side ranges with MemMap Dflag
With this commit we allow a XBar to print the memory map of the
address ranges it responds to.
This can be switched on via the new MemMap debug flag.
A new image is drawn every time there is a change in the memory
map during simulation (for example with PCI devices their
address ranges are setup via PCI Bars during the enumeration
phase / system bringup, and those are not available at construction
time)
These images are hence printed in the outdir (m5out) with the
following name
<xbar.name()>.curTick().jpg
So a single simulation might end up with different pictures of
the same xbar, showing the evolution of the xbar memory map
throughout time
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: Ife9174bc2904dcf44663fbc31db831019dc68749
---
M src/mem/SConscript
M src/mem/xbar.cc
M src/mem/xbar.hh
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/src/mem/SConscript b/src/mem/SConscript
index cf7adc8..bd3cf47 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -122,6 +122,7 @@
DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
DebugFlag('LLSC')
DebugFlag('MemCtrl')
+DebugFlag('MemMap')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 41ad585..7fe6955 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -46,11 +46,15 @@
#include "mem/xbar.hh"
#include "base/logging.hh"
+#include "base/output.hh"
#include "base/trace.hh"
#include "debug/AddrRanges.hh"
#include "debug/Drain.hh"
+#include "debug/MemMap.hh"
#include "debug/XBar.hh"
+#include "python/pybind11/mem.hh"
+
BaseXBar::BaseXBar(const BaseXBarParams &p)
: ClockedObject(p),
frontendLatency(p.frontend_latency),
@@ -511,6 +515,11 @@
}
}
+ // Draw the xbar memory ranges if debug flag is set
+ if (DTRACE(MemMap)) {
+ drawMemRanges();
+ }
+
// tell all our neighbouring memory-side ports that our address
// ranges have changed
for (const auto& port: cpuSidePorts)
@@ -518,6 +527,30 @@
}
}
+void
+BaseXBar::drawMemRanges() const
+{
+ const std::string filename = simout.resolve(
+ csprintf("%s.%d.jpg", name(), curTick()));
+
+ std::vector<AddrRange> ranges;
+ std::vector<std::string> names;
+ for (const auto& port: memSidePorts) {
+ if (port->getId() == defaultPortID)
+ continue;
+
+ auto range_owner = static_cast<ResponsePort&>(
+ port->getPeer()).ownerName();
+
+ for (const auto& range: port->getAddrRanges()) {
+ ranges.push_back(range);
+ names.push_back(range_owner);
+ }
+ }
+
+ drawRanges(filename, ranges, names);
+}
+
AddrRangeList
BaseXBar::getAddrRanges() const
{
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 88be87f..544d2ba 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -352,6 +352,8 @@
*/
AddrRangeList getAddrRanges() const;
+ void drawMemRanges() const;
+
/**
* Calculate the timing parameters for the packet. Updates the
* headerDelay and payloadDelay fields of the packet
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ife9174bc2904dcf44663fbc31db831019dc68749
Gerrit-Change-Number: 41317
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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