Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41734 )
Change subject: arch: Move setting up RegClassInfos into the arches.
......................................................................
arch: Move setting up RegClassInfos into the arches.
Also remove no longer global constants from arch/registers.hh if they
are no longer used locally.
Change-Id: I1d1589db3dd4c51a5ec11e32348d394261e36d17
---
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa_device.cc
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/mips/utility.cc
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/includes.isa
M src/arch/power/registers.hh
M src/arch/power/se_workload.hh
M src/arch/power/utility.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/process.cc
M src/arch/sparc/registers.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/x86/isa.cc
M src/arch/x86/registers.hh
39 files changed, 126 insertions(+), 106 deletions(-)
diff --git a/src/arch/arm/freebsd/se_workload.hh
b/src/arch/arm/freebsd/se_workload.hh
index a228ee0..6f13201 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -34,8 +34,8 @@
#ifndef __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
#define __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
+#include "arch/arm/ccregs.hh"
#include "arch/arm/freebsd/freebsd.hh"
-#include "arch/arm/registers.hh"
#include "arch/arm/se_workload.hh"
#include "params/ArmEmuFreebsd.hh"
#include "sim/syscall_desc.hh"
diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index 276406a..3129b3f 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -36,6 +36,9 @@
*/
#include "arch/arm/htm.hh"
+
+#include "arch/arm/intregs.hh"
+#include "arch/arm/miscregs.hh"
#include "cpu/thread_context.hh"
void
@@ -70,7 +73,7 @@
//tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
nzcv = tc->readMiscReg(MISCREG_NZCV);
daif = tc->readMiscReg(MISCREG_DAIF);
- for (auto n = 0; n < NumIntArchRegs; n++) {
+ for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
x[n] = tc->readIntReg(n);
}
// TODO first detect if FP is enabled at this EL
@@ -97,7 +100,7 @@
//tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
tc->setMiscReg(MISCREG_NZCV, nzcv);
tc->setMiscReg(MISCREG_DAIF, daif);
- for (auto n = 0; n < NumIntArchRegs; n++) {
+ for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
tc->setIntReg(n, x[n]);
}
// TODO first detect if FP is enabled at this EL
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
index 3fa7c1d..d32c58e 100644
--- a/src/arch/arm/htm.hh
+++ b/src/arch/arm/htm.hh
@@ -44,6 +44,7 @@
* ISA-specific types for hardware transactional memory.
*/
+#include "arch/arm/intregs.hh"
#include "arch/arm/registers.hh"
#include "arch/generic/htm.hh"
#include "base/types.hh"
@@ -70,7 +71,7 @@
private:
uint8_t rt; // TSTART destination register
Addr nPc; // Fallback instruction address
- std::array<RegVal, NumIntArchRegs> x; // General purpose registers
+ std::array<RegVal, NUM_ARCH_INTREGS> x; // General purpose registers
std::array<VecRegContainer, NumVecRegs> z; // Vector registers
std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
Addr sp; // Stack Pointer at current EL
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c7f82e0..039224f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -47,6 +47,7 @@
#include "arch/arm/tlbi_op.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
+#include "cpu/reg_class.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "dev/arm/generic_timer.hh"
@@ -65,6 +66,16 @@
pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
+ _regClasses.insert(_regClasses.end(), {
+ { NUM_INTREGS },
+ { 0 },
+ { NumVecRegs },
+ { NumVecRegs * TheISA::NumVecElemPerVecReg },
+ { NumVecPredRegs },
+ { NUM_CCREGS },
+ { NUM_MISCREGS }
+ });
+
miscRegs[MISCREG_SCTLR_RST] = 0;
// Hook up a dummy device if we haven't been configured with a
@@ -484,7 +495,7 @@
RegVal
ISA::readMiscRegNoEffect(int misc_reg) const
{
- assert(misc_reg < NumMiscRegs);
+ assert(misc_reg < NUM_MISCREGS);
const auto ® = lookUpMiscReg[misc_reg]; // bit masks
const auto &map = getMiscIndices(misc_reg);
@@ -810,7 +821,7 @@
void
ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
{
- assert(misc_reg < NumMiscRegs);
+ assert(misc_reg < NUM_MISCREGS);
const auto ® = lookUpMiscReg[misc_reg]; // bit masks
const auto &map = getMiscIndices(misc_reg);
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 7888229..aa2a83a 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -454,7 +454,7 @@
void initializeMiscRegMetadata();
- RegVal miscRegs[NumMiscRegs];
+ RegVal miscRegs[NUM_MISCREGS];
const IntRegIndex *intRegMap;
void
diff --git a/src/arch/arm/isa_device.cc b/src/arch/arm/isa_device.cc
index 5516a2c..009f0a7 100644
--- a/src/arch/arm/isa_device.cc
+++ b/src/arch/arm/isa_device.cc
@@ -37,6 +37,7 @@
#include "arch/arm/isa_device.hh"
+#include "arch/arm/miscregs.hh"
#include "base/logging.hh"
namespace ArmISA
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 7075adb..e82f1a8 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -40,6 +40,7 @@
#include "arch/arm/nativetrace.hh"
+#include "arch/arm/ccregs.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/miscregs.hh"
#include "cpu/thread_context.hh"
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 86bc8e2..b1c1b4d 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -40,7 +40,9 @@
#include "arch/arm/process.hh"
+#include "arch/arm/ccregs.hh"
#include "arch/arm/isa_traits.hh"
+#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "base/loader/elf_object.hh"
#include "base/loader/object_file.hh"
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 0955906..fdbe625 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -41,10 +41,7 @@
#ifndef __ARCH_ARM_REGISTERS_HH__
#define __ARCH_ARM_REGISTERS_HH__
-#include "arch/arm/ccregs.hh"
#include "arch/arm/intregs.hh"
-#include "arch/arm/miscregs.hh"
-#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
@@ -68,14 +65,6 @@
VecPredRegHasPackedRepr, true>;
using VecPredRegContainer = VecPredReg::Container;
-// Constants Related to the number of registers
-// Int, Float, CC, Misc
-const int NumIntArchRegs = NUM_ARCH_INTREGS;
-const int NumIntRegs = NUM_INTREGS;
-const int NumFloatRegs = 0; // Float values are stored in the VecRegs
-const int NumCCRegs = NUM_CCREGS;
-const int NumMiscRegs = NUM_MISCREGS;
-
// Vec, PredVec
// NumFloatV7ArchRegs: This in theory should be 32.
// However in A32 gem5 is splitting double register accesses in two
@@ -89,9 +78,6 @@
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs +
NumVecIntrlvRegs;
const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
- NumVecPredRegs + NumMiscRegs;
-
// Semantically meaningful register indices
const int ReturnValueReg = 0;
const int ReturnValueReg1 = 1;
diff --git a/src/arch/arm/tracers/tarmac_base.cc
b/src/arch/arm/tracers/tarmac_base.cc
index e3364c4..445b151 100644
--- a/src/arch/arm/tracers/tarmac_base.cc
+++ b/src/arch/arm/tracers/tarmac_base.cc
@@ -40,7 +40,7 @@
#include <algorithm>
#include <string>
-#include "config/the_isa.hh"
+#include "arch/arm/miscregs.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
diff --git a/src/arch/arm/tracers/tarmac_record.hh
b/src/arch/arm/tracers/tarmac_record.hh
index e5179ce..870a3fd 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -45,6 +45,7 @@
#include <memory>
+#include "arch/arm/miscregs.hh"
#include "arch/arm/tracers/tarmac_base.hh"
#include "base/printable.hh"
#include "config/the_isa.hh"
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 31408f6..533b339 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -39,8 +39,10 @@
#include <memory>
+#include "arch/arm/ccregs.hh"
#include "arch/arm/faults.hh"
#include "arch/arm/interrupts.hh"
+#include "arch/arm/intregs.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/mmu.hh"
#include "arch/arm/system.hh"
@@ -74,16 +76,13 @@
void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
- for (int i = 0; i < NumIntRegs; i++)
+ for (int i = 0; i < NUM_INTREGS; i++)
dest->setIntRegFlat(i, src->readIntRegFlat(i));
- for (int i = 0; i < NumFloatRegs; i++)
- dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
-
- for (int i = 0; i < NumCCRegs; i++)
+ for (int i = 0; i < NUM_CCREGS; i++)
dest->setCCReg(i, src->readCCReg(i));
- for (int i = 0; i < NumMiscRegs; i++)
+ for (int i = 0; i < NUM_MISCREGS; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
copyVecRegs(src, dest);
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index bd043df..1a12b6a 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -42,6 +42,7 @@
#ifndef __ARCH_ARM_UTILITY_HH__
#define __ARCH_ARM_UTILITY_HH__
+#include "arch/arm/ccregs.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 8b8b2db..5ecf6fb 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -58,17 +58,7 @@
ThreadContext *tc = nullptr;
- RegClasses _regClasses = {
-#if THE_ISA != NULL_ISA
- { TheISA::NumIntRegs },
- { TheISA::NumFloatRegs },
- { TheISA::NumVecRegs },
- { TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg },
- { TheISA::NumVecPredRegs },
- { TheISA::NumCCRegs },
- { TheISA::NumMiscRegs }
-#endif // THE_ISA != NULL_ISA
- };
+ RegClasses _regClasses;
public:
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext
*old_tc) {}
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 7916c4a..98dab66 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -33,6 +33,7 @@
#include "arch/mips/pra_constants.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
+#include "cpu/reg_class.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "params/MipsISA.hh"
@@ -41,7 +42,7 @@
{
std::string
-ISA::miscRegNames[NumMiscRegs] =
+ISA::miscRegNames[MISCREG_NUMREGS] =
{
"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
"Random", "VPEControl", "VPEConf0", "VPEConf1",
@@ -90,17 +91,27 @@
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
- miscRegFile.resize(NumMiscRegs);
- bankType.resize(NumMiscRegs);
+ _regClasses.insert(_regClasses.end(), {
+ { NumIntRegs },
+ { NumFloatRegs },
+ { 1 }, // Not applicable to MIPS.
+ { 2 }, // Not applicable to MIPS.
+ { 1 }, // Not applicable to MIPS.
+ { 0 }, // Not applicable to MIPS.
+ { MISCREG_NUMREGS }
+ });
- for (int i=0; i < NumMiscRegs; i++) {
+ miscRegFile.resize(MISCREG_NUMREGS);
+ bankType.resize(MISCREG_NUMREGS);
+
+ for (int i = 0; i < MISCREG_NUMREGS; i++) {
miscRegFile[i].resize(1);
bankType[i] = perProcessor;
}
- miscRegFile_WriteMask.resize(NumMiscRegs);
+ miscRegFile_WriteMask.resize(MISCREG_NUMREGS);
- for (int i = 0; i < NumMiscRegs; i++) {
+ for (int i = 0; i < MISCREG_NUMREGS; i++) {
miscRegFile_WriteMask[i].push_back(0);
}
@@ -143,7 +154,7 @@
void
ISA::clear()
{
- for (int i = 0; i < NumMiscRegs; i++) {
+ for (int i = 0; i < MISCREG_NUMREGS; i++) {
for (int j = 0; j < miscRegFile[i].size(); j++)
miscRegFile[i][j] = 0;
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index cc05781..e2468ce 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -125,7 +125,7 @@
// and if necessary alert the CPU
void updateCPU(BaseCPU *cpu);
- static std::string miscRegNames[NumMiscRegs];
+ static std::string miscRegNames[MISCREG_NUMREGS];
public:
ISA(const Params &p);
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index a9d2661..67691c9 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -49,11 +49,6 @@
const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI &
LO Regs
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
-const int NumVecRegs = 1; // Not applicable to MIPS
- // (1 to prevent warnings)
-const int NumVecPredRegs = 1; // Not applicable to MIPS
- // (1 to prevent warnings)
-const int NumCCRegs = 0;
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
@@ -266,8 +261,6 @@
MISCREG_NUMREGS
};
-const int NumMiscRegs = MISCREG_NUMREGS;
-
// Not applicable to MIPS
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 78fa3e2..911756f 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -216,11 +216,8 @@
for (int i = 0; i < NumFloatRegs; i++)
dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
// Copy misc. registers
- for (int i = 0; i < NumMiscRegs; i++)
+ for (int i = 0; i < MISCREG_NUMREGS; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
// Copy over the PC State
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index d432636..0aa480c 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -37,6 +37,8 @@
#include "arch/power/isa.hh"
+#include "arch/power/miscregs.hh"
+#include "arch/power/registers.hh"
#include "params/PowerISA.hh"
namespace PowerISA
@@ -44,6 +46,15 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
+ _regClasses.insert(_regClasses.end(), {
+ { NumIntRegs },
+ { NumFloatRegs },
+ { 1 },
+ { 2 },
+ { 1 },
+ { 0 },
+ { NUM_MISCREGS }
+ });
clear();
}
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 3f7968e..7ec9ac7 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -31,6 +31,7 @@
#define __ARCH_POWER_ISA_HH__
#include "arch/generic/isa.hh"
+#include "arch/power/miscregs.hh"
#include "arch/power/registers.hh"
#include "arch/power/types.hh"
#include "base/logging.hh"
@@ -49,7 +50,7 @@
{
protected:
RegVal dummy;
- RegVal miscRegs[NumMiscRegs];
+ RegVal miscRegs[NUM_MISCREGS];
public:
void clear() {}
diff --git a/src/arch/power/isa/includes.isa
b/src/arch/power/isa/includes.isa
index c97aba9..c219d97 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -70,6 +70,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/power/faults.hh"
#include "arch/power/isa_traits.hh"
+#include "arch/power/miscregs.hh"
#include "arch/power/utility.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 2a1aea5..b31f5f3 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -29,10 +29,10 @@
#ifndef __ARCH_POWER_REGISTERS_HH__
#define __ARCH_POWER_REGISTERS_HH__
+#include <cstdint>
+
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/power/miscregs.hh"
-#include "base/types.hh"
namespace PowerISA
{
@@ -62,12 +62,6 @@
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
const int NumFloatRegs = NumFloatArchRegs;
-const int NumVecRegs = 1; // Not applicable to Power
- // (1 to prevent warnings)
-const int NumVecPredRegs = 1; // Not applicable to Power
- // (1 to prevent warnings)
-const int NumCCRegs = 0;
-const int NumMiscRegs = NUM_MISCREGS;
// Semantically meaningful register indices
const int ReturnValueReg = 3;
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index 9bdd0cc..910a271 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -28,6 +28,7 @@
#ifndef __ARCH_POWER_SE_WORKLOAD_HH__
#define __ARCH_POWER_SE_WORKLOAD_HH__
+#include "arch/power/miscregs.hh"
#include "arch/power/registers.hh"
#include "params/PowerSEWorkload.hh"
#include "sim/se_workload.hh"
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index bed0be9..1c68cd9 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -45,9 +45,6 @@
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatReg(i, src->readFloatReg(i));
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 98798e7..073e1de 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -49,7 +49,7 @@
namespace RiscvISA
{
-M5_VAR_USED const std::array<const char *, NumMiscRegs> MiscRegNames = {{
+M5_VAR_USED const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
[MISCREG_PRV] = "PRV",
[MISCREG_ISA] = "ISA",
[MISCREG_VENDORID] = "VENDORID",
@@ -178,7 +178,17 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- miscRegFile.resize(NumMiscRegs);
+ _regClasses.insert(_regClasses.begin(), {
+ { NumIntRegs },
+ { NumFloatRegs },
+ { 1 }, // Not applicable to RISCV
+ { 2 }, // Not applicable to RISCV
+ { 1 }, // Not applicable to RISCV
+ { 0 }, // Not applicable to RISCV
+ { NUM_MISCREGS }
+ });
+
+ miscRegFile.resize(NUM_MISCREGS);
clear();
}
@@ -226,7 +236,7 @@
RegVal
ISA::readMiscRegNoEffect(int misc_reg) const
{
- if (misc_reg > NumMiscRegs || misc_reg < 0) {
+ if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
// Illegal CSR
panic("Illegal CSR index %#x\n", misc_reg);
return -1;
@@ -314,7 +324,7 @@
void
ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
{
- if (misc_reg > NumMiscRegs || misc_reg < 0) {
+ if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
// Illegal CSR
panic("Illegal CSR index %#x\n", misc_reg);
}
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 862259f..bd29bb2 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -111,13 +111,6 @@
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
const int NumFloatRegs = 32;
-const unsigned NumVecRegs = 1; // Not applicable to RISC-V
- // (1 to prevent warnings)
-const int NumVecPredRegs = 1; // Not applicable to RISC-V
- // (1 to prevent warnings)
-
-const int NumCCRegs = 0;
-
// Semantically meaningful register indices
const int ZeroReg = 0;
const int ReturnAddrReg = 1;
@@ -278,7 +271,6 @@
NUM_MISCREGS
};
-const int NumMiscRegs = NUM_MISCREGS;
enum CSRIndex {
CSR_USTATUS = 0x000,
diff --git a/src/arch/sparc/insts/static_inst.cc
b/src/arch/sparc/insts/static_inst.cc
index 467b38f..65a38ff 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -29,6 +29,10 @@
#include "arch/sparc/insts/static_inst.hh"
+#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/registers.hh"
+#include "base/bitunion.hh"
+
namespace SparcISA
{
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 02708b8..18646fa 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -32,6 +32,7 @@
#include "arch/generic/interrupts.hh"
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
#include "arch/sparc/registers.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index ba3839b..12e2908 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -31,6 +31,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/decoder.hh"
#include "arch/sparc/interrupts.hh"
+#include "arch/sparc/miscregs.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
@@ -61,6 +62,15 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
+ _regClasses.insert(_regClasses.end(), {
+ { NumIntRegs },
+ { NumFloatRegs },
+ { 1 }, // Not applicable for SPARC
+ { 2 }, // Not applicable for SPARC
+ { 1 }, // Not applicable for SPARC
+ { 0 }, // Not applicable for SPARC
+ { NumMiscRegs }
+ });
clear();
}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index a58cd85..2d75b0a 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -33,7 +33,7 @@
#include <string>
#include "arch/generic/isa.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/miscregs.hh"
#include "arch/sparc/types.hh"
#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
diff --git a/src/arch/sparc/isa/includes.isa
b/src/arch/sparc/isa/includes.isa
index 1cef0fc..c2c44a7 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -47,6 +47,7 @@
#include "arch/sparc/insts/unimp.hh"
#include "arch/sparc/insts/unknown.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
#include "arch/sparc/registers.hh"
#include "base/condcodes.hh"
#include "base/logging.hh"
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 0923eeb..191cbf2 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -31,6 +31,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/handlers.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/types.hh"
#include "base/loader/elf_object.hh"
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 0602176..1404a1d 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -31,7 +31,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/sparc/miscregs.hh"
#include "arch/sparc/sparc_traits.hh"
#include "base/types.hh"
@@ -94,17 +93,10 @@
const int SyscallPseudoReturnReg = INTREG_O1;
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
-const int NumVecRegs = 1; // Not applicable to SPARC
- // (1 to prevent warnings)
-const int NumVecPredRegs = 1; // Not applicable to SPARC
- // (1 to prevent warnings)
-const int NumCCRegs = 0;
const int NumFloatRegs = 64;
const int NumFloatArchRegs = NumFloatRegs;
-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
} // namespace SparcISA
#endif
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index a2988c6..10c5c1f 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -124,6 +124,7 @@
#include <csignal>
#include <string>
+#include "arch/sparc/miscregs.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 46e03e3..4fc25b6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -33,6 +33,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/faults.hh"
#include "arch/sparc/interrupts.hh"
+#include "arch/sparc/miscregs.hh"
#include "arch/sparc/mmu.hh"
#include "arch/sparc/registers.hh"
#include "base/bitfield.hh"
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index a0c0f8b..e606d16 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -205,9 +205,6 @@
dest->setFloatReg(i, src->readFloatReg(i));
}
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 8ec3e10..053258f 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -30,7 +30,7 @@
#define __ARCH_SPARC_UTILITY_HH__
#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/miscregs.hh"
#include "arch/sparc/tlb.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index f568f01..640422d 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -30,6 +30,10 @@
#include "arch/x86/decoder.hh"
#include "arch/x86/mmu.hh"
+#include "arch/x86/registers.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "params/X86ISA.hh"
@@ -104,7 +108,7 @@
{
// Blank everything. 0 might not be an appropriate value for some
things,
// but it is for most.
- memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
+ memset(regVal, 0, NUM_MISCREGS * sizeof(RegVal));
// If some state should be non-zero after a reset, set those values
here.
regVal[MISCREG_CR0] = 0x0000000060000010ULL;
@@ -134,6 +138,17 @@
{
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
+
+ _regClasses.insert(_regClasses.end(), {
+ { NumIntRegs },
+ { NumFloatRegs },
+ { 1 }, // Not applicable to X86
+ { 2 }, // Not applicable to X86
+ { 1 }, // Not applicable to X86
+ { NUM_CCREGS },
+ { NUM_MISCREGS },
+ });
+
clear();
}
@@ -409,13 +424,13 @@
void
ISA::serialize(CheckpointOut &cp) const
{
- SERIALIZE_ARRAY(regVal, NumMiscRegs);
+ SERIALIZE_ARRAY(regVal, NUM_MISCREGS);
}
void
ISA::unserialize(CheckpointIn &cp)
{
- UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
+ UNSERIALIZE_ARRAY(regVal, NUM_MISCREGS);
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a29f1b8..572fa3d 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -49,8 +49,6 @@
namespace X86ISA
{
-const int NumMiscRegs = NUM_MISCREGS;
-
const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs +
NumImplicitIntRegs;
const int NumCCRegs = NUM_CCREGS;
@@ -68,14 +66,9 @@
FP_Reg_Base = 128,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
- Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
+ Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
};
-const int NumVecRegs = 1; // Not applicable to x86
- // (1 to prevent warnings)
-const int NumVecPredRegs = 1; // Not applicable to x86
- // (1 to prevent warnings)
-
// semantically meaningful register indices
//There is no such register in X86
const int ZeroReg = NUM_INTREGS;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d1589db3dd4c51a5ec11e32348d394261e36d17
Gerrit-Change-Number: 41734
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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