Oh, also, while implementing everything in this new doc would/will be a pretty big undertaking, I think forcing operands in the ISA descriptions to be explicitly sources or destinations but not both would be a major improvement. For most registers that should be pretty trivial (they are already called things like "Dest" or "Src1"), and for the rest the change should just be a lot of find/replace style changes. That could be a first step towards what's in the doc and could be done immediately, independent of anything else.
Gabe On Mon, Feb 22, 2021 at 11:57 PM Gabe Black <[email protected]> wrote: > Hey folks.I have a design doc for a moderate in scope but significant in > impact rework of how instruction execution and tracing work in gem5. This > is something I've been thinking about for a while, but threw together just > now to get it out there: > > > https://docs.google.com/document/d/1IqxBYr_arZq5G51oqmXoL5I9HiiwWMQ_t-rvHA78YPE/edit?usp=sharing > > This is strongly informed by an earlier design doc I wrote about how > registers are handled here: > > > https://docs.google.com/document/d/1O_u_Xq14TgreYThuZcbM3kuXFCrKvaFHA2O9poCeHSk/edit#heading=h.r067bn3rmydo > > It is a lot more narrowly scoped though, focusing only on operands and > instruction execution at the StaticInst level, but also extends beyond what > was described in that original doc. > > I'm biased of course, but I think there's a lot of value in reworking > things as described in the doc. Please take a look at let me know what you > think. > > Gabe >
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