Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41860 )
Change subject: mem-ruby: fix SimpleNetwork WeightBased routing
......................................................................
mem-ruby: fix SimpleNetwork WeightBased routing
Individual link weights are propagated to the routing algorithms and
WeightBased routing now uses this information to select the output
link when multiple routing options exist.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I86a4deb610a1b94abf745e9ef249961fb52e9800
Signed-off-by: Tiago Mück <[email protected]>
---
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
M src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
M src/mem/ruby/network/simple/routing/WeightBased.cc
M src/mem/ruby/network/simple/routing/WeightBased.hh
8 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index de3547d..63203bd 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -89,13 +89,15 @@
void
PerfectSwitch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- const PortDirection &dst_inport)
+ const PortDirection &dst_inport,
+ int link_weight)
{
// Add to routing unit
m_switch->getRoutingUnit().addOutPort(m_out.size(),
out,
routing_table_entry,
- dst_inport);
+ dst_inport,
+ link_weight);
m_out.push_back(out);
}
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh
b/src/mem/ruby/network/simple/PerfectSwitch.hh
index 9b67527..fe32c7f 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -74,7 +74,8 @@
void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- const PortDirection &dst_inport);
+ const PortDirection &dst_inport,
+ int link_weight);
int getInLinks() const { return m_in.size(); }
int getOutLinks() const { return m_out.size(); }
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index aa618d0..c5da257 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -115,7 +115,8 @@
}
m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
- routing_table_entry[0],
simple_link->m_latency,
+ routing_table_entry[0],
+ simple_link->m_latency, 0,
simple_link->m_bw_multiplier);
}
@@ -142,6 +143,7 @@
m_switches[dest]->addInPort(simple_link->m_buffers);
m_switches[src]->addOutPort(simple_link->m_buffers,
routing_table_entry[0],
simple_link->m_latency,
+ simple_link->m_weight,
simple_link->m_bw_multiplier,
dst_inport);
// Maitain a global list of buffers (used for functional accesses only)
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index 0f0849c..224f8bc 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -79,7 +79,8 @@
void
Switch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- Cycles link_latency, int bw_multiplier,
+ Cycles link_latency, int link_weight,
+ int bw_multiplier,
PortDirection dst_inport)
{
const std::vector<int> &physical_vnets_channels =
@@ -117,7 +118,7 @@
// Hook the queues to the PerfectSwitch
perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
- dst_inport);
+ dst_inport, link_weight);
// Hook the queues to the Throttle
throttles.back().addLinks(intermediateBuffers, out);
diff --git a/src/mem/ruby/network/simple/Switch.hh
b/src/mem/ruby/network/simple/Switch.hh
index 2b2ba5f..50a9eac 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -86,7 +86,7 @@
void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- Cycles link_latency, int bw_multiplier,
+ Cycles link_latency, int link_weight, int
bw_multiplier,
PortDirection dst_inport = "");
void resetStats();
diff --git a/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
b/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
index 49140b8..830c341 100644
--- a/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
+++ b/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
@@ -65,7 +65,8 @@
virtual void addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction) = 0;
+ const PortDirection &direction,
+ int link_weight) = 0;
struct RouteInfo {
const NetDest m_destinations;
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.cc
b/src/mem/ruby/network/simple/routing/WeightBased.cc
index 3918642..2dd19cc 100644
--- a/src/mem/ruby/network/simple/routing/WeightBased.cc
+++ b/src/mem/ruby/network/simple/routing/WeightBased.cc
@@ -49,13 +49,15 @@
WeightBased::addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction)
+ const PortDirection &direction,
+ int link_weight)
{
assert(link_id == m_links.size());
m_links.push_back(new LinkInfo{link_id,
routing_table_entry,
m_out_buffer,
- (int)link_id});
+ 0, link_weight});
+ sortLinks();
}
void
@@ -70,7 +72,7 @@
// Don't adaptively route
// Makes sure ordering is reset
for (auto link : m_links)
- link->m_order = (int) link->m_link_id;
+ link->m_order = 0;
} else {
// Find how clogged each link is
for (auto link : m_links) {
@@ -85,11 +87,7 @@
link->m_order = value;
}
}
-
- std::sort(m_links.begin(), m_links.end(),
- [](const LinkInfo* a, const LinkInfo* b) {
- return a->m_order < b->m_order;
- });
+ sortLinks();
}
findRoute(msg, m_links, out_links);
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.hh
b/src/mem/ruby/network/simple/routing/WeightBased.hh
index 6cb4a82..dda00df 100644
--- a/src/mem/ruby/network/simple/routing/WeightBased.hh
+++ b/src/mem/ruby/network/simple/routing/WeightBased.hh
@@ -57,7 +57,8 @@
void addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction);
+ const PortDirection &direction,
+ int link_weight);
void route(const Message &msg,
int vnet,
@@ -72,9 +73,24 @@
const NetDest m_routing_entry;
const std::vector<MessageBuffer*> m_out_buffers;
int m_order;
+ int m_weight;
};
std::vector<LinkInfo*> m_links;
+
+ void sortLinks() {
+ std::sort(m_links.begin(), m_links.end(),
+ [](const LinkInfo* a, const LinkInfo* b) {
+ if (a->m_order == b->m_order){
+ if (a->m_weight == b->m_weight)
+ return a->m_link_id < b->m_link_id;
+ else
+ return a->m_weight < b->m_weight;
+ } else {
+ return a->m_order < b->m_order;
+ }
+ });
+ }
};
#endif // __MEM_RUBY_NETWORK_SIMPLE_WEIGHTBASEDROUTINGUNIT_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I86a4deb610a1b94abf745e9ef249961fb52e9800
Gerrit-Change-Number: 41860
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück <[email protected]>
Gerrit-MessageType: newchange
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