Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41859 )
Change subject: mem-ruby: refactor SimpleNetwork buffers
......................................................................
mem-ruby: refactor SimpleNetwork buffers
This removes the int_link_buffers param from SimpleNetwork. Internal
link buffers are now created as children of SimpleIntLink objects.
This results in a cleaner configuration and simplifies some code in
SimpleNetwork.cc.
setup_buffers is also split between Switch.setup_buffers and
SimpleIntLink.setup_buffers for clarity.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I68ad36ec0e682b8d5600c2950bcb56debe186af3
Signed-off-by: Tiago Mück <[email protected]>
---
M src/mem/ruby/network/simple/SimpleLink.cc
M src/mem/ruby/network/simple/SimpleLink.hh
M src/mem/ruby/network/simple/SimpleLink.py
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
M src/mem/ruby/network/simple/SimpleNetwork.py
6 files changed, 103 insertions(+), 52 deletions(-)
diff --git a/src/mem/ruby/network/simple/SimpleLink.cc
b/src/mem/ruby/network/simple/SimpleLink.cc
index 52d5822..12c311d 100644
--- a/src/mem/ruby/network/simple/SimpleLink.cc
+++ b/src/mem/ruby/network/simple/SimpleLink.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -52,6 +64,8 @@
// endpoint bandwidth multiplier - message size multiplier ratio,
// determines the link bandwidth in bytes
m_bw_multiplier = p.bandwidth_factor;
+
+ m_buffers = p.buffers;
}
void
diff --git a/src/mem/ruby/network/simple/SimpleLink.hh
b/src/mem/ruby/network/simple/SimpleLink.hh
index d3050b2..52c21cb 100644
--- a/src/mem/ruby/network/simple/SimpleLink.hh
+++ b/src/mem/ruby/network/simple/SimpleLink.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -67,6 +79,7 @@
void print(std::ostream& out) const;
int m_bw_multiplier;
+ std::vector<MessageBuffer*> m_buffers;
};
inline std::ostream&
diff --git a/src/mem/ruby/network/simple/SimpleLink.py
b/src/mem/ruby/network/simple/SimpleLink.py
index 89d823b..3d66375 100644
--- a/src/mem/ruby/network/simple/SimpleLink.py
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2011 Advanced Micro Devices, Inc.
# All rights reserved.
#
@@ -26,8 +38,10 @@
from m5.params import *
from m5.proxy import *
+from m5.util import fatal
from m5.SimObject import SimObject
from m5.objects.BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.MessageBuffer import MessageBuffer
class SimpleExtLink(BasicExtLink):
type = 'SimpleExtLink'
@@ -36,3 +50,23 @@
class SimpleIntLink(BasicIntLink):
type = 'SimpleIntLink'
cxx_header = "mem/ruby/network/simple/SimpleLink.hh"
+
+ # Buffers for this internal link.
+ # One buffer is allocated per vnet when setup_buffers is called.
+ # These are created by setup_buffers and the user should not
+ # set these manually.
+ buffers = VectorParam.MessageBuffer("Buffers for int_links")
+
+ def setup_buffers(self, network):
+ if hasattr(self, 'buffers') > 0:
+ fatal("User should not manually set links' \
+ in_buffers or out_buffers")
+ # Note that all SimpleNetwork MessageBuffers are currently ordered
+
+ # The network needs number_of_virtual_networks buffers per
+ # in and out port
+ buffers = []
+ for i in range(int(network.number_of_virtual_networks)):
+ buffers.append(MessageBuffer(ordered = True,
+ buffer_size =
network.vnet_buffer_size(i)))
+ self.buffers = buffers
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index a0ea2d1..aa618d0 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -65,9 +65,6 @@
s->init_net_ptr(this);
}
- m_int_link_buffers = p.int_link_buffers;
- m_num_connected_buffers = 0;
-
const std::vector<int> &physical_vnets_channels =
params().physical_vnets_channels;
const std::vector<int> &physical_vnets_bandwidth =
@@ -139,25 +136,17 @@
PortDirection src_outport,
PortDirection dst_inport)
{
- // Create a set of new MessageBuffers
- std::vector<MessageBuffer*> queues(m_virtual_networks);
-
- for (int i = 0; i < m_virtual_networks; i++) {
- // allocate a buffer
- assert(m_num_connected_buffers < m_int_link_buffers.size());
- MessageBuffer* buffer_ptr =
m_int_link_buffers[m_num_connected_buffers];
- m_num_connected_buffers++;
- queues[i] = buffer_ptr;
- }
-
// Connect it to the two switches
SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
- m_switches[dest]->addInPort(queues);
- m_switches[src]->addOutPort(queues, routing_table_entry[0],
+ m_switches[dest]->addInPort(simple_link->m_buffers);
+ m_switches[src]->addOutPort(simple_link->m_buffers,
routing_table_entry[0],
simple_link->m_latency,
simple_link->m_bw_multiplier,
dst_inport);
+ // Maitain a global list of buffers (used for functional accesses only)
+ m_int_link_buffers.insert(m_int_link_buffers.end(),
+ simple_link->m_buffers.begin(), simple_link->m_buffers.end());
}
void
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh
b/src/mem/ruby/network/simple/SimpleNetwork.hh
index bba9990..28dc353 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.hh
+++ b/src/mem/ruby/network/simple/SimpleNetwork.hh
@@ -103,7 +103,6 @@
std::vector<Switch*> m_switches;
std::vector<MessageBuffer*> m_int_link_buffers;
- int m_num_connected_buffers;
const int m_buffer_size;
const int m_endpoint_bandwidth;
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py
b/src/mem/ruby/network/simple/SimpleNetwork.py
index e812f08..3bea9e2 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -39,6 +39,7 @@
from m5.params import *
from m5.proxy import *
+from m5.util import fatal
from m5.SimObject import SimObject
from m5.objects.Network import RubyNetwork
from m5.objects.BasicRouter import BasicRouter
@@ -47,10 +48,9 @@
class SimpleNetwork(RubyNetwork):
type = 'SimpleNetwork'
cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh"
- buffer_size = Param.Int(0,
- "default buffer size; 0 indicates infinite buffering")
+ buffer_size = Param.Int(0, "default internal buffer size for links and\
+ routers; 0 indicates infinite buffering")
endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor")
- int_link_buffers = VectorParam.MessageBuffer("Buffers for int_links")
# Set to emulate multiple channels for each vnet.
# If not set, all vnets share the same physical channel.
@@ -65,7 +65,7 @@
# Gets the size of the message buffers associated to a vnet
# If physical_vnets_channels is set we just multiply the size of the
- # buffers as SimpleNetwork does not actually creates multiple physival
+ # buffers as SimpleNetwork does not actually creates multiple physical
# channels per vnet
def vnet_buffer_size(self, vnet):
if len(self.physical_vnets_channels) == 0:
@@ -74,39 +74,11 @@
return self.buffer_size * self.physical_vnets_channels[vnet]
def setup_buffers(self):
- # Note that all SimpleNetwork MessageBuffers are currently ordered
- network_buffers = []
+ # Setup internal buffers for links and routers
for link in self.int_links:
- # The network needs number_of_virtual_networks buffers per
- # int_link port
- for i in range(int(self.number_of_virtual_networks)):
- network_buffers.append(MessageBuffer(ordered = True,
- buffer_size =
self.vnet_buffer_size(i)))
- network_buffers.append(MessageBuffer(ordered = True,
- buffer_size =
self.vnet_buffer_size(i)))
- self.int_link_buffers = network_buffers
-
- # Also add buffers for all router-link connections
+ link.setup_buffers(self)
for router in self.routers:
- router_buffers = []
- # Add message buffers to routers at the end of each
- # unidirectional internal link
- for link in self.int_links:
- if link.dst_node == router:
- for i in range(int(self.number_of_virtual_networks)):
- router_buffers.append(MessageBuffer(ordered = True,
- allow_zero_latency = True,
- buffer_size =
self.vnet_buffer_size(i)))
-
- # Add message buffers to routers for each external link
connection
- for link in self.ext_links:
- # Routers can only be int_nodes on ext_links
- if link.int_node in self.routers:
- for i in range(int(self.number_of_virtual_networks)):
- router_buffers.append(MessageBuffer(ordered = True,
- allow_zero_latency = True,
- buffer_size =
self.vnet_buffer_size(i)))
- router.port_buffers = router_buffers
+ router.setup_buffers(self)
class BaseRoutingUnit(SimObject):
@@ -126,8 +98,38 @@
cxx_header = 'mem/ruby/network/simple/Switch.hh'
virt_nets = Param.Int(Parent.number_of_virtual_networks,
"number of virtual networks")
+
+ # Internal port buffers used between the PerfectSwitch and
+ # Throttle objects. There is one buffer per virtual network
+ # and per output port.
+ # These are created by setup_buffers and the user should not
+ # set these manually.
port_buffers = VectorParam.MessageBuffer("Port buffers")
routing_unit = Param.BaseRoutingUnit(
WeightBased(adaptive_routing = False),
"Routing strategy to be used")
+
+ def setup_buffers(self, network):
+ if hasattr(self, 'port_buffers') > 0:
+ fatal("User should not manually set routers' port_buffers")
+ router_buffers = []
+ # Add message buffers to routers at the end of each
+ # unidirectional internal link
+ for link in network.int_links:
+ if link.dst_node == self:
+ for i in range(int(network.number_of_virtual_networks)):
+ router_buffers.append(MessageBuffer(ordered = True,
+ allow_zero_latency = True,
+ buffer_size =
network.vnet_buffer_size(i)))
+
+ # Add message buffers to routers for each external link connection
+ for link in network.ext_links:
+ # Routers can only be int_nodes on ext_links
+ if link.int_node == self:
+ for i in range(int(network.number_of_virtual_networks)):
+ router_buffers.append(MessageBuffer(ordered = True,
+ allow_zero_latency = True,
+ buffer_size =
network.vnet_buffer_size(i)))
+
+ self.port_buffers = router_buffers
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I68ad36ec0e682b8d5600c2950bcb56debe186af3
Gerrit-Change-Number: 41859
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück <[email protected]>
Gerrit-MessageType: newchange
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