Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41894 )
Change subject: WIP
......................................................................
WIP
Change-Id: I0ccbd634cc3374d28c0e79ea82cef39f1ba2c141
---
M src/arch/generic/isa.hh
M src/arch/x86/isa.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
9 files changed, 76 insertions(+), 31 deletions(-)
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 2fc8df4..78303ac 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -45,6 +45,15 @@
class ThreadContext;
+class RegisterClassInfo
+{
+ protected:
+ size_t _size = 0;
+
+ public:
+ size_t size() const { return _size; }
+};
+
class BaseISA : public SimObject
{
protected:
@@ -70,6 +79,8 @@
{
return initVecRegRenameMode();
}
+
+ const RegisterClassInfo ®isterClassInfo(RegClass reg_class) const =
0;
};
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 5d31d87..a653bbb 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -53,6 +53,16 @@
std::string vendorString;
+ RegisterClassInfo regClassInfo[NumRegClasses] = {
+ { NumIntRegs },
+ { NumFloatRegs },
+ { 1 },
+ { 1 },
+ { 1 },
+ { NumCCRegs },
+ { NUM_MISCREGS }
+ };
+
public:
void clear();
@@ -115,6 +125,12 @@
void setThreadContext(ThreadContext *_tc) override;
std::string getVendorString() const;
+
+ const RegisterClassInfo &
+ registerClassInfo(RegClass reg_class) const override
+ {
+ return regClassInfo[reg_class];
+ }
};
}
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index ed582ad..0f33954 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -168,6 +168,9 @@
for (ThreadID tid = 0; tid < params.numThreads; tid++) {
std::string tid_str = std::to_string(tid);
+ ThreadContext *tc = cpu.threads[tid]->getTC();
+ const int numRegs = ;
+
/* Input Buffers */
inputBuffer.push_back(
InputBuffer<ForwardInstData>(
@@ -175,7 +178,11 @@
params.executeInputBufferSize));
/* Scoreboards */
- scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
+ scoreboard.emplace_back(name_ + ".scoreboard" + tid_str,
+ tc->registerClassInfo(IntRegClass).size(),
+ TheISA::NumCCRegs, TheISA::NumFloatRegs,
+ TheISA::NumVecRegs, TheISA::NumVecElemPerVecReg,
+ TheISA::NumVecPredRegs);
/* In-flight instruction records */
executeInfo[tid].inFlightInsts = new Queue<QueuedInst,
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index c0846c7..459d693 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -57,31 +57,24 @@
switch (reg.classValue())
{
case IntRegClass:
- scoreboard_index = reg.index();
+ scoreboard_index = intRegOffset + reg.index();
ret = true;
break;
case FloatRegClass:
- scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
- reg.index();
+ scoreboard_index = floatRegOffset + reg.index();
ret = true;
break;
case VecRegClass:
- scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
- TheISA::NumFloatRegs + reg.index();
- ret = true;
- break;
case VecElemClass:
- scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
- TheISA::NumFloatRegs + reg.flatIndex();
+ scoreboard_index = vecRegOffset + reg.index();
ret = true;
break;
case VecPredRegClass:
- scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
- TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index();
+ scoreboard_index = vecPredRegOffset + reg.index();
ret = true;
break;
case CCRegClass:
- scoreboard_index = TheISA::NumIntRegs + reg.index();
+ scoreboard_index = ccRegOffset + reg.index();
ret = true;
break;
case MiscRegClass:
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index aab0b2b..e7e7293 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -60,6 +60,11 @@
class Scoreboard : public Named
{
public:
+ const unsigned intRegOffset = 0;
+ const unsigned ccRegOffset;
+ const unsigned floatRegOffset;
+ const unsigned vecRegOffset;
+ const unsigned vecPredRegOffset;
/** The number of registers in the Scoreboard. These
* are just the integer, CC and float registers packed
* together with integer regs in the range [0,NumIntRegs-1],
@@ -92,12 +97,17 @@
std::vector<InstSeqNum> writingInst;
public:
- Scoreboard(const std::string &name) :
+ Scoreboard(const std::string &name,
+ unsigned numIntRegs, unsigned numCcRegs, unsigned numFloatRegs,
+ unsigned numVecRegs, unsigned numVecElemPerReg,
+ unsigned numVecPredRegs) :
Named(name),
- numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
- TheISA::NumFloatRegs +
- (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
- TheISA::NumVecPredRegs),
+ ccRegOffset(numIntRegs),
+ floatRegOffset(ccRegOffset + numCcRegs),
+ vecRegOffset(floatRegOffset + numFloatRegs),
+ vecPredRegOffset(vecRegOffset + numVecRegs),
+ numRegs(numIntRegs + numCcRegs + numFloatRegs +
+ (numVecRegs * numVecElemPerReg) + numVecPredRegs),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
fuIndices(numRegs, 0),
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index f15be91..d293ba0 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -67,6 +67,7 @@
Process *_process, BaseMMU *_mmu,
BaseISA *_isa)
: ThreadState(_cpu, _thread_num, _process),
+ intRegs(_isa->registerClassInfo(IntRegClass).size()),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
@@ -80,6 +81,7 @@
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
BaseMMU *_mmu, BaseISA *_isa)
: ThreadState(_cpu, _thread_num, NULL),
+ intRegs(_isa->registerClassInfo(IntRegClass).size()),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 7a13825..9d206b6 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -42,8 +42,6 @@
#ifndef __CPU_SIMPLE_THREAD_HH__
#define __CPU_SIMPLE_THREAD_HH__
-#include <array>
-
#include "arch/decoder.hh"
#include "arch/generic/htm.hh"
#include "arch/generic/mmu.hh"
@@ -94,7 +92,7 @@
protected:
std::array<RegVal, TheISA::NumFloatRegs> floatRegs;
- std::array<RegVal, TheISA::NumIntRegs> intRegs;
+ std::vector<RegVal> intRegs;
std::array<TheISA::VecRegContainer, TheISA::NumVecRegs> vecRegs;
std::array<TheISA::VecPredRegContainer, TheISA::NumVecPredRegs>
vecPredRegs;
@@ -270,8 +268,8 @@
readIntReg(RegIndex reg_idx) const override
{
int flatIndex = isa->flattenIntIndex(reg_idx);
- assert(flatIndex < TheISA::NumIntRegs);
- uint64_t regVal(readIntRegFlat(flatIndex));
+ assert(flatIndex < intRegs.size());
+ uint64_t regVal = readIntRegFlat(flatIndex);
DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
@@ -442,7 +440,7 @@
setIntReg(RegIndex reg_idx, RegVal val) override
{
int flatIndex = isa->flattenIntIndex(reg_idx);
- assert(flatIndex < TheISA::NumIntRegs);
+ assert(flatIndex < intRegs.size());
DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
reg_idx, flatIndex, val);
setIntRegFlat(flatIndex, val);
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 16db818..9983c9f 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -57,7 +57,7 @@
DPRINTF(Context, "Comparing thread contexts\n");
// First loop through the integer registers.
- for (int i = 0; i < TheISA::NumIntRegs; ++i) {
+ for (int i = 0; i < registerClassInfo(IntRegClass).size(); ++i) {
RegVal t1 = one->readIntReg(i);
RegVal t2 = two->readIntReg(i);
if (t1 != t2)
@@ -161,10 +161,11 @@
}
SERIALIZE_CONTAINER(vecPredRegs);
- RegVal intRegs[TheISA::NumIntRegs];
- for (int i = 0; i < TheISA::NumIntRegs; ++i)
+ const size_t numIntRegs = registerClassInfo(IntRegClass).size();
+ RegVal intRegs[numIntRegs];
+ for (int i = 0; i < numIntRegs; ++i)
intRegs[i] = tc.readIntRegFlat(i);
- SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+ SERIALIZE_ARRAY(intRegs, numIntRegs);
if (TheISA::NumCCRegs) {
RegVal ccRegs[TheISA::NumCCRegs];
@@ -201,9 +202,10 @@
tc.setVecPredRegFlat(i, vecPredRegs[i]);
}
- RegVal intRegs[TheISA::NumIntRegs];
- UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
- for (int i = 0; i < TheISA::NumIntRegs; ++i)
+ const size_t numIntRegs = registerClassInfo(IntRegClass).size();
+ RegVal intRegs[numIntRegs];
+ UNSERIALIZE_ARRAY(intRegs, numIntRegs);
+ for (int i = 0; i < numIntRegs; ++i)
tc.setIntRegFlat(i, intRegs[i]);
if (TheISA::NumCCRegs) {
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index c1c951d..ba49390 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -296,6 +296,12 @@
// Same with st cond failures.
virtual Counter readFuncExeInst() const = 0;
+ const RegisterClassInfo &
+ registerClassInfo(RegClass reg_class)
+ {
+ return getIsaPtr()->registerClassInfo(reg_class);
+ }
+
// This function exits the thread context in the CPU and returns
// 1 if the CPU has no more active threads (meaning it's OK to exit);
// Used in syscall-emulation mode when a thread calls the exit
syscall.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41894
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ccbd634cc3374d28c0e79ea82cef39f1ba2c141
Gerrit-Change-Number: 41894
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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