[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,misc: Add missing overrides for clang compilation

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41913 )

Change subject: arch-riscv,misc: Add missing overrides for clang compilation
......................................................................
arch-riscv,misc: Add missing overrides for clang compilation

The Clang compiler returns "missing override" errors without these.

Change-Id: I62af6c338b000123c924f0b3205551579bd5aeb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41913
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
Reviewed-by: Hoa Nguyen <hoangu...@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/riscv/isa.hh
M src/dev/riscv/clint.hh
M src/dev/riscv/rtc.hh
3 files changed, 7 insertions(+), 5 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 1c5dac3..7f03a17 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -97,8 +97,8 @@

     bool inUserMode() const override { return true; }

-    void serialize(CheckpointOut &cp) const;
-    void unserialize(CheckpointIn &cp);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;

     ISA(const Params &p);
 };
diff --git a/src/dev/riscv/clint.hh b/src/dev/riscv/clint.hh
index 7b1745c..1f213ce 100644
--- a/src/dev/riscv/clint.hh
+++ b/src/dev/riscv/clint.hh
@@ -139,7 +139,8 @@
      * SimObject functions
      */
     void init() override;
-    Port & getPort(const std::string &if_name, PortID idx=InvalidPortID);
+    Port & getPort(const std::string &if_name,
+                   PortID idx=InvalidPortID) override;
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

diff --git a/src/dev/riscv/rtc.hh b/src/dev/riscv/rtc.hh
index bfd9071..42a2d29 100644
--- a/src/dev/riscv/rtc.hh
+++ b/src/dev/riscv/rtc.hh
@@ -70,9 +70,10 @@

     RiscvRTC(const Params &params);

-    Port & getPort(const std::string &if_name, PortID idx=InvalidPortID);
+    Port & getPort(const std::string &if_name,
+                   PortID idx=InvalidPortID) override;

-    void startup();
+    void startup() override;

     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62af6c338b000123c924f0b3205551579bd5aeb4
Gerrit-Change-Number: 41913
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Peter Yuen <petery....@huawei.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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