Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41999 )
Change subject: arch,cpu: Separate printing and serialization of VecPredReg.
......................................................................
arch,cpu: Separate printing and serialization of VecPredReg.
This is equivalent to what was done with VecReg recently.
Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
---
M src/arch/generic/vec_pred_reg.hh
M src/cpu/o3/regfile.hh
M src/cpu/simple_thread.hh
3 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/src/arch/generic/vec_pred_reg.hh
b/src/arch/generic/vec_pred_reg.hh
index 6db0e1e..cdf5eb5 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -44,6 +44,7 @@
#include <vector>
#include "base/cprintf.hh"
+#include "sim/serialize_handlers.hh"
template <size_t NumBits>
class VecPredRegContainer;
@@ -145,18 +146,13 @@
friend std::ostream&
operator<<(std::ostream& os, const MyClass& p)
{
- // 0-sized is not allowed
- os << '[' << p.container[0];
- for (int i = 0; i < p.NUM_BITS; ++i) {
- os << " " << (p.container[i] ? 1 : 0);
- }
- os << ']';
+ // Size must be greater than 0.
+ for (int i = 0; i < NUM_BITS; i++)
+ ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+ ccprintf(os, "]");
return os;
}
- /// Returns a string representation of the register content.
- const std::string print() const { return csprintf("%s", *this); }
-
/// Returns true if the first active element of the register is true.
/// @param mask Input mask used to filter the predicates to be tested.
/// @param actual_num_elems Actual number of vector elements
considered for
@@ -318,18 +314,18 @@
}
}
- /// Returns a string representation of the register content.
- const std::string print() const { return csprintf("%s", *this); }
-
friend std::ostream&
- operator<<(std::ostream& os, const MyClass& v)
+ operator<<(std::ostream& os, const MyClass& p)
{
- for (auto b: v.container) {
- os << csprintf("%d", b);
- }
+ // Size must be greater than 0.
+ for (int i = 0; i < NumBits; i++)
+ ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+ ccprintf(os, "]");
return os;
}
+ friend ShowParam<VecPredRegContainer<NumBits>>;
+
/// Create a view of this container.
///
/// If NumElems is provided, the size of the container is
bounds-checked,
@@ -359,17 +355,29 @@
/// @}
};
-/// Helper functions used for serialization/de-serialization
template <size_t NumBits>
-inline bool
-to_number(const std::string& value, VecPredRegContainer<NumBits>& p)
+struct ParseParam<VecPredRegContainer<NumBits>>
{
- int i = 0;
- for (const auto& c: value) {
- p[i] = (c == '1');
+ static bool
+ parse(const std::string &s, VecPredRegContainer<NumBits> &value)
+ {
+ int i = 0;
+ for (const auto& c: s)
+ value[i++] = (c == '1');
+ return true;
}
- return true;
-}
+};
+
+template <size_t NumBits>
+struct ShowParam<VecPredRegContainer<NumBits>>
+{
+ static void
+ show(std::ostream &os, const VecPredRegContainer<NumBits> &value)
+ {
+ for (auto b: value.container)
+ ccprintf(os, "%d", b);
+ }
+};
/// Dummy type aliases and constants for architectures that do not
implement
/// vector predicate registers.
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 6c6b9b3..65a5338 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -238,7 +238,7 @@
DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
"data %s\n", int(phys_reg->index()),
- vecPredRegFile[phys_reg->index()].print());
+ vecPredRegFile[phys_reg->index()]);
return vecPredRegFile[phys_reg->index()];
}
@@ -322,7 +322,7 @@
assert(phys_reg->isVecPredPhysReg());
DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
- int(phys_reg->index()), val.print());
+ int(phys_reg->index()), val);
vecPredRegFile[phys_reg->index()] = val;
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8f65ea3..7a4a4b7 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -330,7 +330,7 @@
const TheISA::VecPredRegContainer& regVal =
readVecPredRegFlat(flatIndex);
DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
- reg.index(), flatIndex, regVal.print());
+ reg.index(), flatIndex, regVal);
return regVal;
}
@@ -343,7 +343,7 @@
getWritableVecPredRegFlat(flatIndex);
DPRINTF(VecPredRegs,
"Reading predicate reg %d (%d) as %s for modify.\n",
- reg.index(), flatIndex, regVal.print());
+ reg.index(), flatIndex, regVal);
return regVal;
}
@@ -410,7 +410,7 @@
assert(flatIndex < TheISA::NumVecPredRegs);
setVecPredRegFlat(flatIndex, val);
DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
- reg.index(), flatIndex, val.print());
+ reg.index(), flatIndex, val);
}
void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Gerrit-Change-Number: 41999
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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