[gem5-dev] Change in gem5/gem5[develop]: cpu: Extract stage classes from O3's SimpleCPUPolicy.

Gabe Black (Gerrit) via gem5-dev Wed, 03 Mar 2021 09:18:40 -0800

Gabe Black has uploaded this change for review. (https://gem5-review.googlesource.com/c/public/gem5/+/42098 )


Change subject: cpu: Extract stage classes from O3's SimpleCPUPolicy.
......................................................................

cpu: Extract stage classes from O3's SimpleCPUPolicy.

Use the target types directly without that layer of indirection. This
also narrows the scope of some includes.

Change-Id: I152f2ce0684781a9b61bd9d5a38620c39a4c60e8
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/cpu_policy.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/rename.hh
11 files changed, 41 insertions(+), 48 deletions(-)



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 3418bd3..f4c1305 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -46,6 +46,7 @@
 #include "base/statistics.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/timebuf.hh"
 #include "enums/CommitPolicy.hh"
@@ -95,9 +96,6 @@
     typedef typename CPUPol::IEWStruct IEWStruct;
     typedef typename CPUPol::RenameStruct RenameStruct;

-    typedef typename CPUPol::Fetch Fetch;
-    typedef typename CPUPol::IEW IEW;
-
     typedef O3ThreadState<Impl> Thread;

     /** Overall commit status. Used to determine if the CPU can deschedule
@@ -162,13 +160,13 @@
     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);

     /** Sets the pointer to the IEW stage. */
-    void setIEWStage(IEW *iew_stage);
+    void setIEWStage(DefaultIEW<Impl> *iew_stage);

     /** The pointer to the IEW stage. Used solely to ensure that
      * various events (traps, interrupts, syscalls) do not occur until
      * all stores have written back.
      */
-    IEW *iewStage;
+    DefaultIEW<Impl> *iewStage;

     /** Sets pointer to list of active threads. */
     void setActiveThreads(std::list<ThreadID> *at_ptr);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 2cb24c0..c72c83c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -291,7 +291,7 @@

 template <class Impl>
 void
-DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
+DefaultCommit<Impl>::setIEWStage(DefaultIEW<Impl> *iew_stage)
 {
     iewStage = iew_stage;
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 9519d3b..2bc1fd4 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -54,8 +54,13 @@
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
+#include "cpu/o3/commit.hh"
 #include "cpu/o3/cpu_policy.hh"
+#include "cpu/o3/decode.hh"
+#include "cpu/o3/fetch.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
+#include "cpu/o3/rename.hh"
 #include "cpu/o3/scoreboard.hh"
 #include "cpu/o3/thread_state.hh"
 #include "cpu/activity.hh"
@@ -538,19 +543,19 @@

   protected:
     /** The fetch stage. */
-    typename CPUPolicy::Fetch fetch;
+    DefaultFetch<Impl> fetch;

     /** The decode stage. */
-    typename CPUPolicy::Decode decode;
+    DefaultDecode<Impl> decode;

     /** The dispatch stage. */
-    typename CPUPolicy::Rename rename;
+    DefaultRename<Impl> rename;

     /** The issue/execute/writeback stages. */
-    typename CPUPolicy::IEW iew;
+    DefaultIEW<Impl> iew;

     /** The commit stage. */
-    typename CPUPolicy::Commit commit;
+    DefaultCommit<Impl> commit;

     /** The rename mode of the vector registers */
     Enums::VecRegRenameMode vecMode;
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
index 82dcd09..c5af880 100644
--- a/src/cpu/o3/cpu_policy.hh
+++ b/src/cpu/o3/cpu_policy.hh
@@ -31,17 +31,12 @@
 #define __CPU_O3_CPU_POLICY_HH__

 #include "cpu/o3/comm.hh"
-#include "cpu/o3/commit.hh"
-#include "cpu/o3/decode.hh"
-#include "cpu/o3/fetch.hh"
 #include "cpu/o3/free_list.hh"
-#include "cpu/o3/iew.hh"
 #include "cpu/o3/inst_queue.hh"
 #include "cpu/o3/lsq.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "cpu/o3/mem_dep_unit.hh"
 #include "cpu/o3/regfile.hh"
-#include "cpu/o3/rename.hh"
 #include "cpu/o3/rename_map.hh"
 #include "cpu/o3/rob.hh"
 #include "cpu/o3/store_set.hh"
@@ -73,17 +68,6 @@
     /** Typedef for the thread-specific LSQ units. */
     typedef ::LSQUnit<Impl> LSQUnit;

-    /** Typedef for fetch. */
-    typedef DefaultFetch<Impl> Fetch;
-    /** Typedef for decode. */
-    typedef DefaultDecode<Impl> Decode;
-    /** Typedef for rename. */
-    typedef DefaultRename<Impl> Rename;
-    /** Typedef for Issue/Execute/Writeback. */
-    typedef DefaultIEW<Impl> IEW;
-    /** Typedef for commit. */
-    typedef DefaultCommit<Impl> Commit;
-
     /** The struct for communication between fetch and decode. */
     typedef DefaultFetchDefaultDecode<Impl> FetchStruct;

diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index f395554..b750354 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -51,6 +51,7 @@
 #include "base/types.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/dep_graph.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/op_class.hh"
 #include "cpu/timebuf.hh"
@@ -86,7 +87,6 @@
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;

-    typedef typename Impl::CPUPol::IEW IEW;
     typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
     typedef typename Impl::CPUPol::IssueStruct IssueStruct;
     typedef typename Impl::CPUPol::TimeStruct TimeStruct;
@@ -122,7 +122,7 @@
     };

     /** Constructs an IQ. */
-    InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
+    InstructionQueue(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
                      const DerivO3CPUParams &params);

     /** Destructs the IQ. */
@@ -281,7 +281,7 @@
     MemInterface *dcacheInterface;

     /** Pointer to IEW stage. */
-    IEW *iewStage;
+    DefaultIEW<Impl> *iewStage;

/** The memory dependence unit, which tracks/predicts memorydependences

      *  between instructions.
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index c992d77..5d1b305 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -83,8 +83,8 @@
 }

 template <class Impl>
-InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
-                                         const DerivO3CPUParams &params)
+InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr,
+        DefaultIEW<Impl> *iew_ptr, const DerivO3CPUParams &params)
     : cpu(cpu_ptr),
       iewStage(iew_ptr),
       fuPool(params.fuPool),
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 2eaa701..95bf258 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -65,13 +65,15 @@
 class FullO3CPU;

 template <class Impl>
+class DefaultIEW;
+
+template <class Impl>
 class LSQ

 {
   public:
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::CPUPol::IEW IEW;
     typedef typename Impl::CPUPol::LSQUnit LSQUnit;

     class LSQRequest;
@@ -853,7 +855,8 @@
     };

     /** Constructs an LSQ with the given parameters. */
-    LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, const DerivO3CPUParams &params);
+    LSQ(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+            const DerivO3CPUParams &params);
     ~LSQ() { }

     /** Returns the name of the LSQ. */
@@ -1112,7 +1115,7 @@
     O3CPU *cpu;

     /** The IEW stage pointer. */
-    IEW *iewStage;
+    DefaultIEW<Impl> *iewStage;

     /** Is D-cache blocked? */
     bool cacheBlocked() const;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 31c1beb..acd4a69 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -48,6 +48,7 @@

 #include "base/logging.hh"
 #include "cpu/o3/cpu.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/lsq.hh"
 #include "debug/Drain.hh"
@@ -58,7 +59,8 @@
 #include "params/DerivO3CPU.hh"

 template <class Impl>

-LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, const DerivO3CPUParams&params)

+LSQ<Impl>::LSQ(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+        const DerivO3CPUParams &params)
     : cpu(cpu_ptr), iewStage(iew_ptr),
       _cacheBlocked(false),
       cacheStorePorts(params.cacheStorePorts), usedStorePorts(0),
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index dbe15e6..1257448 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -62,6 +62,9 @@
 struct DerivO3CPUParams;
 #include "base/circular_queue.hh"

+template <class Impl>
+class DefaultIEW;
+
 /**
  * Class that implements the actual LQ and SQ for each specific
  * thread.  Both are circular queues; load entries are freed upon
@@ -82,7 +85,6 @@

     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::CPUPol::IEW IEW;
     typedef typename Impl::CPUPol::LSQ LSQ;
     typedef typename Impl::CPUPol::IssueStruct IssueStruct;

@@ -232,8 +234,8 @@
     }

     /** Initializes the LSQ unit with the specified number of entries. */
-    void init(O3CPU *cpu_ptr, IEW *iew_ptr, const DerivO3CPUParams &params,
-            LSQ *lsq_ptr, unsigned id);
+    void init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+            const DerivO3CPUParams &params, LSQ *lsq_ptr, unsigned id);

     /** Returns the name of the LSQ unit. */
     std::string name() const;
@@ -408,7 +410,7 @@
     O3CPU *cpu;

     /** Pointer to the IEW stage. */
-    IEW *iewStage;
+    DefaultIEW<Impl> *iewStage;

     /** Pointer to the LSQ. */
     LSQ *lsq;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 8244222..71d02f1 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -215,7 +215,7 @@

 template<class Impl>
 void
-LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr,
+LSQUnit<Impl>::init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
         const DerivO3CPUParams &params, LSQ *lsq_ptr, unsigned id)
 {
     lsqID = id;
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index 4867a12..f582789 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -47,6 +47,8 @@

 #include "base/statistics.hh"
 #include "config/the_isa.hh"
+#include "cpu/o3/commit.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/timebuf.hh"
 #include "sim/probe/probe.hh"
@@ -80,9 +82,6 @@
     typedef typename CPUPol::TimeStruct TimeStruct;
     typedef typename CPUPol::FreeList FreeList;
     typedef typename CPUPol::RenameMap RenameMap;
-    // These are used only for initialization.
-    typedef typename CPUPol::IEW IEW;
-    typedef typename CPUPol::Commit Commit;

     // A deque is used to queue the instructions. Barrier insts must
     // be added to the front of the queue, which is the only reason for
@@ -147,19 +146,19 @@
     void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);

     /** Sets pointer to IEW stage. Used only for initialization. */
-    void setIEWStage(IEW *iew_stage)
+    void setIEWStage(DefaultIEW<Impl> *iew_stage)
     { iew_ptr = iew_stage; }

     /** Sets pointer to commit stage. Used only for initialization. */
-    void setCommitStage(Commit *commit_stage)
+    void setCommitStage(DefaultCommit<Impl> *commit_stage)
     { commit_ptr = commit_stage; }

   private:
     /** Pointer to IEW stage. Used only for initialization. */
-    IEW *iew_ptr;
+    DefaultIEW<Impl> *iew_ptr;

     /** Pointer to commit stage. Used only for initialization. */
-    Commit *commit_ptr;
+    DefaultCommit<Impl> *commit_ptr;

   public:
     /** Initializes variables for the stage. */

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42098

To unsubscribe, or for help writing mail filters, visithttps://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I152f2ce0684781a9b61bd9d5a38620c39a4c60e8
Gerrit-Change-Number: 42098
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange

_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu: Extract stage classes from O3's SimpleCPUPolicy.

Reply via email to