Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42104 )
Change subject: cpu: Remove the MemDepPred template parameter from
MemDepUnit.
......................................................................
cpu: Remove the MemDepPred template parameter from MemDepUnit.
Hard code this to StoreSet, the only value ever used with this
parameter. If the dependency predictor needs to be updatable, there
should be a well defined interface for it which can be connected at run
time.
Change-Id: Ie30a742eac98220cc39679d26ada5d08099659a0
---
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/mem_dep_unit.cc
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
4 files changed, 63 insertions(+), 67 deletions(-)
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 8cfbfeb..3c97e64 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -291,7 +291,7 @@
/** The memory dependence unit, which tracks/predicts memory
dependences
* between instructions.
*/
- MemDepUnit<StoreSet, Impl> memDepUnit[O3MaxThreads];
+ MemDepUnit<Impl> memDepUnit[O3MaxThreads];
/** The queue to the execute stage. Issued instructions will be
written
* into it.
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index 21c91d7..963d614 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -28,20 +28,15 @@
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/mem_dep_unit_impl.hh"
-#include "cpu/o3/store_set.hh"
#ifdef DEBUG
template <>
-int
-MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_count = 0;
+int MemDepUnit<O3CPUImpl>::MemDepEntry::memdep_count = 0;
template <>
-int
-MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_insert = 0;
+int MemDepUnit<O3CPUImpl>::MemDepEntry::memdep_insert = 0;
template <>
-int
-MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
+int MemDepUnit<O3CPUImpl>::MemDepEntry::memdep_erase = 0;
#endif
-// Force instantation of memory dependency unit using store sets and
-// O3CPUImpl.
-template class MemDepUnit<StoreSet, O3CPUImpl>;
+// Force instantation of memory dependency unit using O3CPUImpl.
+template class MemDepUnit<O3CPUImpl>;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index cd81939..0b8a852 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -51,6 +51,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/limits.hh"
+#include "cpu/o3/store_set.hh"
#include "debug/MemDepUnit.hh"
struct SNHash {
@@ -81,7 +82,7 @@
* utilize. Thus this class should be most likely be rewritten for other
* dependence prediction schemes.
*/
-template <class MemDepPred, class Impl>
+template <class Impl>
class MemDepUnit
{
protected:
@@ -257,7 +258,7 @@
* this unit what instruction the newly added instruction is dependent
* upon.
*/
- MemDepPred depPred;
+ StoreSet depPred;
/** Sequence numbers of outstanding load barriers. */
std::unordered_set<InstSeqNum> loadBarrierSNs;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index 1efb91c..de5764b 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -52,15 +52,15 @@
#include "debug/MemDepUnit.hh"
#include "params/DerivO3CPU.hh"
-template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::MemDepUnit()
+template <class Impl>
+MemDepUnit<Impl>::MemDepUnit()
: iqPtr(NULL),
stats(nullptr)
{
}
-template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::MemDepUnit(const DerivO3CPUParams ¶ms)
+template <class Impl>
+MemDepUnit<Impl>::MemDepUnit(const DerivO3CPUParams ¶ms)
: _name(params.name + ".memdepunit"),
depPred(params.store_set_clear_period, params.SSITSize,
params.LFSTSize),
@@ -70,8 +70,8 @@
DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
}
-template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
+template <class Impl>
+MemDepUnit<Impl>::~MemDepUnit()
{
for (ThreadID tid = 0; tid < O3MaxThreads; tid++) {
@@ -95,9 +95,9 @@
#endif
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::init(
+MemDepUnit<Impl>::init(
const DerivO3CPUParams ¶ms, ThreadID tid, FullO3CPU<Impl> *cpu)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
@@ -112,8 +112,8 @@
cpu->addStatGroup(stats_group_name.c_str(), &stats);
}
-template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::
+template <class Impl>
+MemDepUnit<Impl>::
MemDepUnitStats::MemDepUnitStats(Stats::Group *parent)
: Stats::Group(parent),
ADD_STAT(insertedLoads, UNIT_COUNT,
@@ -125,9 +125,9 @@
{
}
-template <class MemDepPred, class Impl>
+template <class Impl>
bool
-MemDepUnit<MemDepPred, Impl>::isDrained() const
+MemDepUnit<Impl>::isDrained() const
{
bool drained = instsToReplay.empty()
&& memDepHash.empty()
@@ -138,9 +138,9 @@
return drained;
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::drainSanityCheck() const
+MemDepUnit<Impl>::drainSanityCheck() const
{
assert(instsToReplay.empty());
assert(memDepHash.empty());
@@ -150,9 +150,9 @@
assert(memDepHash.empty());
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::takeOverFrom()
+MemDepUnit<Impl>::takeOverFrom()
{
// Be sure to reset all state.
loadBarrierSNs.clear();
@@ -160,16 +160,16 @@
depPred.clear();
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
+MemDepUnit<Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
{
iqPtr = iq_ptr;
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::insertBarrierSN(const O3DynInstPtr
&barr_inst)
+MemDepUnit<Impl>::insertBarrierSN(const O3DynInstPtr &barr_inst)
{
InstSeqNum barr_sn = barr_inst->seqNum;
@@ -200,9 +200,9 @@
}
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::insert(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::insert(const O3DynInstPtr &inst)
{
ThreadID tid = inst->threadNumber;
@@ -311,9 +311,9 @@
}
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::insertNonSpec(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::insertNonSpec(const O3DynInstPtr &inst)
{
insertBarrier(inst);
@@ -333,9 +333,9 @@
}
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::insertBarrier(const O3DynInstPtr &barr_inst)
+MemDepUnit<Impl>::insertBarrier(const O3DynInstPtr &barr_inst)
{
ThreadID tid = barr_inst->threadNumber;
@@ -356,9 +356,9 @@
insertBarrierSN(barr_inst);
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::regsReady(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::regsReady(const O3DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Marking registers as ready for "
"instruction PC %s [sn:%lli].\n",
@@ -379,9 +379,9 @@
}
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::nonSpecInstReady(const O3DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Marking non speculative "
"instruction PC %s as ready [sn:%lli].\n",
@@ -392,16 +392,16 @@
moveToReady(inst_entry);
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::reschedule(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::reschedule(const O3DynInstPtr &inst)
{
instsToReplay.push_back(inst);
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::replay()
+MemDepUnit<Impl>::replay()
{
O3DynInstPtr temp_inst;
@@ -420,9 +420,9 @@
}
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::completed(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::completed(const O3DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
inst->pcState(), inst->seqNum);
@@ -444,9 +444,9 @@
#endif
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::completeInst(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::completeInst(const O3DynInstPtr &inst)
{
wakeDependents(inst);
completed(inst);
@@ -476,9 +476,9 @@
}
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::wakeDependents(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::wakeDependents(const O3DynInstPtr &inst)
{
// Only stores, atomics and barriers have dependents.
if (!inst->isStore() && !inst->isAtomic() && !inst->isReadBarrier() &&
@@ -513,9 +513,9 @@
inst_entry->dependInsts.clear();
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
+MemDepUnit<Impl>::squash(const InstSeqNum &squashed_num,
ThreadID tid)
{
if (!instsToReplay.empty()) {
@@ -565,9 +565,9 @@
depPred.squash(squashed_num, tid);
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::violation(const O3DynInstPtr &store_inst,
+MemDepUnit<Impl>::violation(const O3DynInstPtr &store_inst,
const O3DynInstPtr &violating_load)
{
DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
@@ -577,9 +577,9 @@
depPred.violation(store_inst->instAddr(), violating_load->instAddr());
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::issue(const O3DynInstPtr &inst)
+MemDepUnit<Impl>::issue(const O3DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
inst->instAddr(), inst->seqNum);
@@ -587,9 +587,9 @@
depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
}
-template <class MemDepPred, class Impl>
-inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
-MemDepUnit<MemDepPred, Impl>::findInHash(const O3DynInstConstPtr &inst)
+template <class Impl>
+typename MemDepUnit<Impl>::MemDepEntryPtr &
+MemDepUnit<Impl>::findInHash(const O3DynInstConstPtr &inst)
{
MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
@@ -598,9 +598,9 @@
return (*hash_it).second;
}
-template <class MemDepPred, class Impl>
-inline void
-MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
+template <class Impl>
+void
+MemDepUnit<Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
{
DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
"to the ready list.\n", woken_inst_entry->inst->seqNum);
@@ -611,9 +611,9 @@
}
-template <class MemDepPred, class Impl>
+template <class Impl>
void
-MemDepUnit<MemDepPred, Impl>::dumpLists()
+MemDepUnit<Impl>::dumpLists()
{
for (ThreadID tid = 0; tid < O3MaxThreads; tid++) {
cprintf("Instruction list %i size: %i\n",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie30a742eac98220cc39679d26ada5d08099659a0
Gerrit-Change-Number: 42104
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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