Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42353 )
Change subject: arch-x86: Use regIdx() instead of creating an InstRegIndex
directly.
......................................................................
arch-x86: Use regIdx() instead of creating an InstRegIndex directly.
The microcode assembler provides a regIdx() wrapper which will wrap
constants with an appropriate InstRegIndex constructor without having to
do so manually.
Change-Id: I782289bdfcbe4e3552ff44123dfce2ccc86f9266
---
M
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
M
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
M src/arch/x86/isa/insts/system/msrs.py
M src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 554d93f..b59d85f 100644
---
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -35,24 +35,24 @@
microcode = '''
def macroop STMXCSR_M {
- rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ rdval t1, regIdx("MISCREG_MXCSR")
st t1, seg, sib, disp
};
def macroop STMXCSR_P {
- rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ rdval t1, regIdx("MISCREG_MXCSR")
rdip t7
st t1, seg, riprel, disp
};
def macroop LDMXCSR_M {
ld t1, seg, sib, disp
- wrval "InstRegIndex(MISCREG_MXCSR)", t1
+ wrval regIdx("MISCREG_MXCSR"), t1
};
def macroop LDMXCSR_P {
rdip t7
ld t1, seg, riprel, disp
- wrval "InstRegIndex(MISCREG_MXCSR)", t1
+ wrval regIdx("MISCREG_MXCSR"), t1
};
'''
diff --git
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
index c46f849..c519b56 100644
---
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
+++
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
@@ -43,16 +43,16 @@
'''
loadXMMRegTemplate = '''
- ldfp "InstRegIndex(FLOATREG_XMM_LOW(%(idx)i))", seg, %(mode)s, \
+ ldfp regIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i", dataSize=8
- ldfp "InstRegIndex(FLOATREG_XMM_HIGH(%(idx)i))", seg, %(mode)s, \
+ ldfp regIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i + 8", dataSize=8
'''
storeXMMRegTemplate = '''
- stfp "InstRegIndex(FLOATREG_XMM_LOW(%(idx)i))", seg, %(mode)s, \
+ stfp regIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i", dataSize=8
- stfp "InstRegIndex(FLOATREG_XMM_HIGH(%(idx)i))", seg, %(mode)s, \
+ stfp regIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i + 8", dataSize=8
'''
@@ -80,10 +80,10 @@
rdxftw t1
st t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=1
- rdval t1, "InstRegIndex(MISCREG_FOP)"
+ rdval t1, regIdx("MISCREG_FOP")
st t1, seg, %(mode)s, "DISPLACEMENT + 6", dataSize=2
- rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ rdval t1, regIdx("MISCREG_MXCSR")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 8", dataSize=4
# MXCSR_MASK, software assumes the default (0xFFBF) if 0.
@@ -92,24 +92,24 @@
""" + storeAllDataRegs
fxsave32Template = """
- rdval t1, "InstRegIndex(MISCREG_FIOFF)"
+ rdval t1, regIdx("MISCREG_FIOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=4
- rdval t1, "InstRegIndex(MISCREG_FISEG)"
+ rdval t1, regIdx("MISCREG_FISEG")
st t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=2
- rdval t1, "InstRegIndex(MISCREG_FOOFF)"
+ rdval t1, regIdx("MISCREG_FOOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=4
- rdval t1, "InstRegIndex(MISCREG_FOSEG)"
+ rdval t1, regIdx("MISCREG_FOSEG")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
""" + fxsaveCommonTemplate
fxsave64Template = """
- rdval t1, "InstRegIndex(MISCREG_FIOFF)"
+ rdval t1, regIdx("MISCREG_FIOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=8
- rdval t1, "InstRegIndex(MISCREG_FOOFF)"
+ rdval t1, regIdx("MISCREG_FOOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8
""" + fxsaveCommonTemplate
@@ -126,36 +126,36 @@
wrxftw t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 6", dataSize=2
- wrval "InstRegIndex(MISCREG_FOP)", t1
+ wrval regIdx("MISCREG_FOP"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 8", dataSize=4
- wrval "InstRegIndex(MISCREG_MXCSR)", t1
+ wrval regIdx("MISCREG_MXCSR"), t1
""" + loadAllDataRegs
fxrstor32Template = """
ld t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=4
- wrval "InstRegIndex(MISCREG_FIOFF)", t1
+ wrval regIdx("MISCREG_FIOFF"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=2
- wrval "InstRegIndex(MISCREG_FISEG)", t1
+ wrval regIdx("MISCREG_FISEG"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=4
- wrval "InstRegIndex(MISCREG_FOOFF)", t1
+ wrval regIdx("MISCREG_FOOFF"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
- wrval "InstRegIndex(MISCREG_FOSEG)", t1
+ wrval regIdx("MISCREG_FOSEG"), t1
""" + fxrstorCommonTemplate
fxrstor64Template = """
limm t2, 0, dataSize=8
ld t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=8
- wrval "InstRegIndex(MISCREG_FIOFF)", t1
- wrval "InstRegIndex(MISCREG_FISEG)", t2
+ wrval regIdx("MISCREG_FIOFF"), t1
+ wrval regIdx("MISCREG_FISEG"), t2
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8
- wrval "InstRegIndex(MISCREG_FOOFF)", t1
- wrval "InstRegIndex(MISCREG_FOSEG)", t2
+ wrval regIdx("MISCREG_FOOFF"), t1
+ wrval regIdx("MISCREG_FOSEG"), t2
""" + fxrstorCommonTemplate
microcode = '''
diff --git a/src/arch/x86/isa/insts/system/msrs.py
b/src/arch/x86/isa/insts/system/msrs.py
index 2c29681..280a534 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -71,6 +71,6 @@
rdtsc t1
mov rax, rax, t1, dataSize=4
srli rdx, t1, 32, dataSize=8
- rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4
+ rdval rcx, regIdx("MISCREG_TSC_AUX"), dataSize=4
};
'''
diff --git
a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
index 21a1a8c..e47ccac 100644
--- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
+++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
@@ -39,19 +39,19 @@
wrval ftw, t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=4
- wrval "InstRegIndex(MISCREG_FIOFF)", t1
+ wrval regIdx("MISCREG_FIOFF"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=2
- wrval "InstRegIndex(MISCREG_FISEG)", t1
+ wrval regIdx("MISCREG_FISEG"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 2", dataSize=2
- wrval "InstRegIndex(MISCREG_FOP)", t1
+ wrval regIdx("MISCREG_FOP"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 20", dataSize=4
- wrval "InstRegIndex(MISCREG_FOOFF)", t1
+ wrval regIdx("MISCREG_FOOFF"), t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 24", dataSize=2
- wrval "InstRegIndex(MISCREG_FOSEG)", t1
+ wrval regIdx("MISCREG_FOSEG"), t1
"""
fnstenvTemplate = """
@@ -63,24 +63,24 @@
st t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=2
srli t1, t1, 11, dataSize=2
andi t1, t1, 0x7, dataSize=2
- wrval "InstRegIndex(MISCREG_X87_TOP)", t1
+ wrval regIdx("MISCREG_X87_TOP"), t1
rdval t1, ftw
st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=2
- rdval t1, "InstRegIndex(MISCREG_FIOFF)"
+ rdval t1, regIdx("MISCREG_FIOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=4
- rdval t1, "InstRegIndex(MISCREG_FISEG)"
+ rdval t1, regIdx("MISCREG_FISEG")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=2
- rdval t1, "InstRegIndex(MISCREG_FOP)"
+ rdval t1, regIdx("MISCREG_FOP")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 2", dataSize=2
- rdval t1, "InstRegIndex(MISCREG_FOOFF)"
+ rdval t1, regIdx("MISCREG_FOOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 20", dataSize=4
- rdval t1, "InstRegIndex(MISCREG_FOSEG)"
+ rdval t1, regIdx("MISCREG_FOSEG")
st t1, seg, %(mode)s, "DISPLACEMENT + 24", dataSize=2
# Mask exceptions
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I782289bdfcbe4e3552ff44123dfce2ccc86f9266
Gerrit-Change-Number: 42353
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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