Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42388 )
Change subject: arch-sparc: Use GuestABI to call pseudo insts.
......................................................................
arch-sparc: Use GuestABI to call pseudo insts.
Rather than decode and call each PsuedoInst function one by one, we can
use a GuestABI which knows how to marshal arguments and return values
and call the pseudoInst dispatch function which will do the work for us,
and make SPARC able to call any pseudo inst, not just the ones it was
hard coded to recognize.
Change-Id: I28192c4feeaf86a77c0f23c5b131929e45ec6d74
---
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/includes.isa
A src/arch/sparc/pseudo_inst_abi.hh
3 files changed, 77 insertions(+), 26 deletions(-)
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index d8d9a27..b6e4ccb 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1001,30 +1001,12 @@
0x81: FailUnimpl::siam();
}
// M5 special opcodes use the reserved IMPDEP2A opcode space
- 0x37: decode M5FUNC {
- format BasicOperate {
- // we have 7 bits of space here to play with...
- 0x21: m5exit({{
- PseudoInst::m5exit(xc->tcBase(), O0);
- }}, No_OpClass, IsNonSpeculative);
- 0x23: m5sum({{
- O0 = PseudoInst::m5sum(xc->tcBase(),
- O0, O1, O2, O3, O4, O5);
- }}, IsNonSpeculative);
- 0x50: m5readfile({{
- O0 = PseudoInst::readfile(xc->tcBase(), O0, O1,
O2);
- }}, IsNonSpeculative);
- 0x51: m5break({{
- PseudoInst::debugbreak(xc->tcBase());
- }}, IsNonSpeculative);
- 0x54: m5panic({{
- panic("M5 panic instruction called at pc = %#x.",
PC);
- }}, No_OpClass, IsNonSpeculative);
- }
- default: Trap::impdep2({{
+ 0x37: BasicOperate::pseudo_inst({{
+ if (!PseudoInst::pseudoInst<SparcPseudoInstABI>(
+ xc->tcBase(), M5FUNC)) {
fault = std::make_shared<IllegalInstruction>();
- }});
- }
+ }
+ }}, No_OpClass, IsNonSpeculative);
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if (target & 0x3) {
diff --git a/src/arch/sparc/isa/includes.isa
b/src/arch/sparc/isa/includes.isa
index 1cef0fc..d68d8fb 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -53,15 +53,16 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh" // some constructors use MemReq flags
+
}};
output decoder {{
#include <algorithm>
#include "arch/sparc/decoder.hh"
-#include "base/loader/symtab.hh"
#include "base/cprintf.hh"
#include "base/fenv.hh"
+#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
@@ -69,13 +70,13 @@
}};
output exec {{
-#include "base/fenv.hh"
-
#include <cmath>
#include <limits>
#include "arch/generic/memhelpers.hh"
#include "arch/sparc/asi.hh"
+#include "arch/sparc/pseudo_inst_abi.hh"
+#include "base/fenv.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/Sparc.hh"
diff --git a/src/arch/sparc/pseudo_inst_abi.hh
b/src/arch/sparc/pseudo_inst_abi.hh
new file mode 100644
index 0000000..446043a
--- /dev/null
+++ b/src/arch/sparc/pseudo_inst_abi.hh
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_SPARC_PSEUDO_INST_ABI_HH__
+#define __ARCH_SPARC_PSEUDO_INST_ABI_HH__
+
+#include "arch/sparc/registers.hh"
+#include "sim/guest_abi.hh"
+
+struct SparcPseudoInstABI
+{
+ using State = int;
+};
+
+namespace GuestABI
+{
+
+template <typename T>
+struct Result<SparcPseudoInstABI, T>
+{
+ static void
+ store(ThreadContext *tc, const T &ret)
+ {
+ // This assumes that all pseudo ops have their return value set
+ // by the pseudo op instruction. This may need to be revisited if
we
+ // modify the pseudo op ABI in util/m5/m5op_x86.S
+ tc->setIntReg(SparcISA::INTREG_O0, ret);
+ }
+};
+
+template <>
+struct Argument<SparcPseudoInstABI, uint64_t>
+{
+ static uint64_t
+ get(ThreadContext *tc, SparcPseudoInstABI::State &state)
+ {
+ panic_if(state >= 6, "Too many psuedo inst arguments.");
+ return tc->readIntReg(SparcISA::INTREG_O0 + state++);
+ }
+};
+
+} // namespace GuestABI
+
+#endif // __ARCH_SPARC_PSEUDO_INST_ABI_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I28192c4feeaf86a77c0f23c5b131929e45ec6d74
Gerrit-Change-Number: 42388
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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