Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42523 )
Change subject: arch-x86: Clean up x86 integer indexes.
......................................................................
arch-x86: Clean up x86 integer indexes.
Instead of having a bunch of implicit integer registers which are
identified only by number, except in the ISA description where there are
operands hard coded to certain numeric offsets into the implicit
registers, and having an independent count of those implicit registers,
just create a set of named indices for the registers we need.
Redefine NUM_INTREGS to be the total number of registers, and
NUM_ARCH_INTREGS to be the number of architectural integer registers.
Instead of using NUM_INTREGS as a coincidental short hand for the first
microop register (since that comes after the architectural ones), and
implicitly knowing that that's the zero register, define an INTREG_T0
constant which at least makes it clear what register we're talking
about, even if it's not clear that the semantics of that register make
it mostly a placeholder.
Change-Id: I5fa41169b9619ea68a50d6d5241ff9a07440bceb
---
M src/arch/x86/emulenv.cc
M src/arch/x86/emulenv.hh
M src/arch/x86/faults.cc
M src/arch/x86/insts/static_inst.cc
M src/arch/x86/isa/microasm.isa
M src/arch/x86/isa/operands.isa
M src/arch/x86/registers.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/x86_traits.hh
9 files changed, 31 insertions(+), 37 deletions(-)
diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc
index 8e080bb..0c19925 100644
--- a/src/arch/x86/emulenv.cc
+++ b/src/arch/x86/emulenv.cc
@@ -54,10 +54,10 @@
//In this special case, we don't use a base. The displacement also
//changes, but that's managed by the decoder.
if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0)
- base = NUM_INTREGS;
+ base = INTREG_T0;
//In -this- special case, we don't use an index.
if (index == INTREG_RSP)
- index = NUM_INTREGS;
+ index = INTREG_T0;
} else {
if (machInst.addrSize == 2) {
unsigned rm = machInst.modRM.rm;
@@ -92,7 +92,7 @@
if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
//Since we need to use a different encoding of this
//instruction anyway, just ignore the base in those cases
- base = NUM_INTREGS;
+ base = INTREG_T0;
}
}
}
diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh
index 1490326..e160b0b 100644
--- a/src/arch/x86/emulenv.hh
+++ b/src/arch/x86/emulenv.hh
@@ -60,8 +60,8 @@
EmulEnv(RegIndex _reg, RegIndex _regm,
int _dataSize, int _addressSize, int _stackSize) :
reg(_reg), regm(_regm), seg(SEGMENT_REG_DS),
- scale(0), index(NUM_INTREGS),
- base(NUM_INTREGS),
+ scale(0), index(INTREG_T0),
+ base(INTREG_T0),
dataSize(_dataSize), addressSize(_addressSize),
stackSize(_stackSize)
{;}
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index a507515..f27db6e 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -184,7 +184,7 @@
{
DPRINTF(Faults, "Init interrupt.\n");
// The otherwise unmodified integer registers should be set to 0.
- for (int index = 0; index < NUM_INTREGS; index++) {
+ for (int index = 0; index < NUM_ARCH_INTREGS; index++) {
tc->setIntReg(index, 0);
}
diff --git a/src/arch/x86/insts/static_inst.cc
b/src/arch/x86/insts/static_inst.cc
index 46d0458..27bba0a 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -210,7 +210,7 @@
ccprintf(os, longFormats[size], "15");
break;
default:
- ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
+ ccprintf(os, microFormats[size], reg_idx - INTREG_MICRO_BEGIN);
}
ccprintf(os, suffix);
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 922452e..bac4902 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -78,7 +78,7 @@
# Add in symbols for the microcode registers
for num in range(16):
- assembler.symbols["t%d" % num] = gpRegIdx("NUM_INTREGS+%d" % num)
+ assembler.symbols["t%d" % num] = gpRegIdx("INTREG_MICRO(%d)" % num)
for num in range(8):
assembler.symbols["ufp%d" % num] = \
fpRegIdx("FLOATREG_MICROFP(%d)" % num)
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 58c2946..1187867 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -56,9 +56,6 @@
let {{
def intReg(idx, id):
return ('IntReg', 'uqw', idx, 'IsInteger', id)
- def impIntReg(idx, id):
- return ('IntReg', 'uqw', 'X86ISA::INTREG_IMPLICIT(%s)' % idx,
- 'IsInteger', id)
def floatReg(idx, id):
return ('FloatReg', 'df', idx, 'IsFloating', id)
def ccReg(idx, id):
@@ -93,12 +90,12 @@
'Data': intReg('data', 6),
'DataLow': intReg('dataLow', 6),
'DataHi': intReg('dataHi', 6),
- 'ProdLow': impIntReg(0, 7),
- 'ProdHi': impIntReg(1, 8),
- 'Quotient': impIntReg(2, 9),
- 'Remainder': impIntReg(3, 10),
- 'Divisor': impIntReg(4, 11),
- 'DoubleBits': impIntReg(5, 11),
+ 'ProdLow': intReg('X86ISA::INTREG_PRODLOW', 7),
+ 'ProdHi': intReg('X86ISA::INTREG_PRODHI', 8),
+ 'Quotient': intReg('X86ISA::INTREG_QUOTIENT', 9),
+ 'Remainder': intReg('X86ISA::INTREG_REMAINDER', 10),
+ 'Divisor': intReg('X86ISA::INTREG_DIVISOR', 11),
+ 'DoubleBits': intReg('X86ISA::INTREG_DOUBLEBITS', 11),
'Rax': intReg('X86ISA::INTREG_RAX', 12),
'Rbx': intReg('X86ISA::INTREG_RBX', 13),
'Rcx': intReg('X86ISA::INTREG_RCX', 14),
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 4832a73..1712f9e 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -50,9 +50,7 @@
{
const int NumMiscRegs = NUM_MISCREGS;
-
-const int NumIntArchRegs = NUM_INTREGS;
-const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs +
NumImplicitIntRegs;
+const int NumIntRegs = NUM_INTREGS;
const int NumCCRegs = NUM_CCREGS;
// Each 128 bit xmm register is broken into two effective 64 bit registers.
@@ -67,7 +65,7 @@
// semantically meaningful register indices
//There is no such register in X86
-const int ZeroReg = NUM_INTREGS;
+const int ZeroReg = INTREG_T0;
const int StackPointerReg = INTREG_RSP;
// Not applicable to x86
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index aa26224..6b588cc 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -144,7 +144,20 @@
INTREG_R15W = INTREG_R15,
INTREG_R15B = INTREG_R15,
- NUM_INTREGS
+ NUM_ARCH_INTREGS,
+
+ INTREG_MICRO_BEGIN = NUM_ARCH_INTREGS,
+ INTREG_T0 = INTREG_MICRO_BEGIN,
+ INTREG_MICRO_END = INTREG_MICRO_BEGIN + NumMicroIntRegs,
+
+ INTREG_PRODLOW,
+ INTREG_PRODHI,
+ INTREG_QUOTIENT,
+ INTREG_REMAINDER,
+ INTREG_DIVISOR,
+ INTREG_DOUBLEBITS,
+
+ NUM_INTREGS,
};
// This needs to be large enough to miss all the other bits of an
index.
@@ -153,13 +166,7 @@
inline static IntRegIndex
INTREG_MICRO(int index)
{
- return (IntRegIndex)(NUM_INTREGS + index);
- }
-
- inline static IntRegIndex
- INTREG_IMPLICIT(int index)
- {
- return (IntRegIndex)(NUM_INTREGS + NumMicroIntRegs + index);
+ return (IntRegIndex)(INTREG_MICRO_BEGIN + index);
}
inline static IntRegIndex
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 6f1c9ae..7d9cedf 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -46,14 +46,6 @@
{
const int NumMicroIntRegs = 16;
- const int NumImplicitIntRegs = 6;
- //1. The lower part of the result of multiplication.
- //2. The upper part of the result of multiplication.
- //3. The quotient from division
- //4. The remainder from division
- //5. The divisor for division
- //6. The register to use for shift doubles
-
const int NumMMXRegs = 8;
const int NumXMMRegs = 16;
const int NumMicroFpRegs = 8;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5fa41169b9619ea68a50d6d5241ff9a07440bceb
Gerrit-Change-Number: 42523
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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