Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43244 )
Change subject: arch-riscv: Fix Clint and SATP write side effects
......................................................................
arch-riscv: Fix Clint and SATP write side effects
Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:
1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).
2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).
Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/pma_checker.cc
M src/dev/riscv/clint.cc
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index aa94942..4a3f5ef 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -92,7 +92,11 @@
CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
csr(FUNCT12), uimm(CSRIMM)
- {}
+ {
+ if (csr == CSR_SATP) {
+ flags[IsSquashAfter] = true;
+ }
+ }
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index d36dc1d..15c5cf9 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -54,7 +54,7 @@
PMAChecker::check(const RequestPtr &req)
{
if (isUncacheable(req->getPaddr(), req->getSize())) {
- req->setFlags(Request::UNCACHEABLE);
+ req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
}
}
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 641ba6f..ced9122 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -64,7 +64,9 @@
for (int context_id = 0; context_id < nThread; context_id++) {
// Update misc reg file
- system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME,
mtime);
+ ISA* isa = dynamic_cast<ISA*>(
+ system->threads[context_id]->getIsaPtr());
+ isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
// Post timer interrupt
uint64_t mtimecmp = registers.mtimecmp[context_id].get();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43244
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Gerrit-Change-Number: 43244
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
