Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39015 )
Change subject: misc: Fix coding style for class-opening braces
......................................................................
misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.
First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:
grep -nrE --exclude-dir=systemc \
"^ *class [A-Za-z].* {$" src/
Then the following commands were run to replace:
<indent level>class X ... {
by:
<indent level>class X ...
<indent level>{
Level 0:
grep -nrl --exclude-dir=systemc
"^class [A-Za-z].* {$" src/ | \
xargs sed -Ei \
's/^class ([A-Za-z].*) \{$/class \1\n\{/g'
Level 1:
grep -nrl --exclude-dir=systemc \
"^ class [A-Za-z].* {$" src/ | \
xargs sed -Ei \
's/^ class ([A-Za-z].*) \{$/ class \1\n \{/g'
and so on.
Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/insts/sve.hh
M src/arch/arm/isa.hh
M src/arch/arm/pmu.hh
M src/arch/arm/table_walker.hh
M src/base/bitunion.test.cc
M src/cpu/o3/fu_pool.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/probe/simple_trace.hh
M src/cpu/pc_event.hh
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_64KB.hh
M src/cpu/pred/multiperspective_perceptron_8KB.hh
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/testers/gpu_ruby_test/episode.hh
M src/dev/hsa/hsa_driver.hh
M src/dev/hsa/hsa_packet_processor.hh
M src/dev/riscv/clint.hh
M src/dev/riscv/hifive.hh
M src/dev/riscv/plic.hh
M src/dev/storage/ide_disk.hh
M src/dev/virtio/base.hh
M src/kern/operatingsystem.hh
M src/mem/abstract_mem.hh
M src/mem/cache/base.hh
M src/mem/cache/cache_blk.hh
M src/mem/cache/mshr.hh
M src/mem/cache/prefetch/associative_set.hh
M src/mem/cache/prefetch/base.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/write_queue_entry.hh
M src/mem/packet_queue.hh
M src/mem/ruby/structures/TBEStorage.hh
M src/mem/ruby/system/CacheRecorder.hh
M src/mem/snoop_filter.hh
M src/sim/futex_map.hh
M src/sim/linear_solver.hh
M src/sim/mathexpr.hh
M src/sim/se_signal.hh
M src/sim/serialize.hh
M src/sim/syscall_desc.hh
M src/sim/syscall_emul_buf.hh
M src/unittest/stattest.cc
46 files changed, 242 insertions(+), 122 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index c0fa29c..ce9ff98 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -53,7 +53,8 @@
const char* svePredTypeToStr(SvePredType pt);
/// Index generation instruction, immediate operands
-class SveIndexIIOp : public ArmStaticInst {
+class SveIndexIIOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
int8_t imm1;
@@ -69,7 +70,8 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
-class SveIndexIROp : public ArmStaticInst {
+class SveIndexIROp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
int8_t imm1;
@@ -85,7 +87,8 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
-class SveIndexRIOp : public ArmStaticInst {
+class SveIndexRIOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -101,7 +104,8 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
-class SveIndexRROp : public ArmStaticInst {
+class SveIndexRROp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -118,7 +122,8 @@
};
// Predicate count SVE instruction.
-class SvePredCountOp : public ArmStaticInst {
+class SvePredCountOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex gp;
@@ -137,7 +142,8 @@
};
// Predicate count SVE instruction (predicated).
-class SvePredCountPredOp : public ArmStaticInst {
+class SvePredCountPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -154,7 +160,8 @@
};
/// While predicate generation SVE instruction.
-class SveWhileOp : public ArmStaticInst {
+class SveWhileOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
bool srcIs32b;
@@ -170,7 +177,8 @@
};
/// Compare and terminate loop SVE instruction.
-class SveCompTermOp : public ArmStaticInst {
+class SveCompTermOp : public ArmStaticInst
+{
protected:
IntRegIndex op1, op2;
@@ -184,7 +192,8 @@
};
/// Unary, constructive, predicated (merging) SVE instruction.
-class SveUnaryPredOp : public ArmStaticInst {
+class SveUnaryPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, gp;
@@ -199,7 +208,8 @@
};
/// Unary, constructive, unpredicated SVE instruction.
-class SveUnaryUnpredOp : public ArmStaticInst {
+class SveUnaryUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1;
@@ -214,7 +224,8 @@
};
/// Unary with wide immediate, constructive, unpredicated SVE instruction.
-class SveUnaryWideImmUnpredOp : public ArmStaticInst {
+class SveUnaryWideImmUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
uint64_t imm;
@@ -231,7 +242,8 @@
};
/// Unary with wide immediate, constructive, predicated SVE instruction.
-class SveUnaryWideImmPredOp : public ArmStaticInst {
+class SveUnaryWideImmPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
uint64_t imm;
@@ -251,7 +263,8 @@
};
/// Binary with immediate, destructive, unpredicated SVE instruction.
-class SveBinImmUnpredConstrOp : public ArmStaticInst {
+class SveBinImmUnpredConstrOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1;
uint64_t imm;
@@ -268,7 +281,8 @@
};
/// Binary with immediate, destructive, predicated (merging) SVE
instruction.
-class SveBinImmPredOp : public ArmStaticInst {
+class SveBinImmPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, gp;
uint64_t imm;
@@ -284,7 +298,8 @@
};
/// Binary with wide immediate, destructive, unpredicated SVE instruction.
-class SveBinWideImmUnpredOp : public ArmStaticInst {
+class SveBinWideImmUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
uint64_t imm;
@@ -301,7 +316,8 @@
};
/// Binary, destructive, predicated (merging) SVE instruction.
-class SveBinDestrPredOp : public ArmStaticInst {
+class SveBinDestrPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op2, gp;
@@ -317,7 +333,8 @@
};
/// Binary, constructive, predicated SVE instruction.
-class SveBinConstrPredOp : public ArmStaticInst {
+class SveBinConstrPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2, gp;
SvePredType predType;
@@ -335,7 +352,8 @@
};
/// Binary, unpredicated SVE instruction with indexed operand
-class SveBinUnpredOp : public ArmStaticInst {
+class SveBinUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
@@ -350,7 +368,8 @@
};
/// Binary, unpredicated SVE instruction
-class SveBinIdxUnpredOp : public ArmStaticInst {
+class SveBinIdxUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
uint8_t index;
@@ -367,7 +386,8 @@
};
/// Predicate logical instruction.
-class SvePredLogicalOp : public ArmStaticInst {
+class SvePredLogicalOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2, gp;
bool isSel;
@@ -384,7 +404,8 @@
};
/// Predicate binary permute instruction.
-class SvePredBinPermOp : public ArmStaticInst {
+class SvePredBinPermOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
@@ -400,7 +421,8 @@
};
/// SVE compare instructions, predicated (zeroing).
-class SveCmpOp : public ArmStaticInst {
+class SveCmpOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, gp, op1, op2;
@@ -416,7 +438,8 @@
};
/// SVE compare-with-immediate instructions, predicated (zeroing).
-class SveCmpImmOp : public ArmStaticInst {
+class SveCmpImmOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, gp, op1;
uint64_t imm;
@@ -433,7 +456,8 @@
};
/// Ternary, destructive, predicated (merging) SVE instruction.
-class SveTerPredOp : public ArmStaticInst {
+class SveTerPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2, gp;
@@ -449,7 +473,8 @@
};
/// Ternary with immediate, destructive, unpredicated SVE instruction.
-class SveTerImmUnpredOp : public ArmStaticInst {
+class SveTerImmUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op2;
uint64_t imm;
@@ -466,7 +491,8 @@
};
/// SVE reductions.
-class SveReducOp : public ArmStaticInst {
+class SveReducOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, gp;
@@ -481,7 +507,8 @@
};
/// SVE ordered reductions.
-class SveOrdReducOp : public ArmStaticInst {
+class SveOrdReducOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, gp;
@@ -496,7 +523,8 @@
};
/// PTRUE, PTRUES.
-class SvePtrueOp : public ArmStaticInst {
+class SvePtrueOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
uint8_t imm;
@@ -512,7 +540,8 @@
};
/// Integer compare SVE instruction.
-class SveIntCmpOp : public ArmStaticInst {
+class SveIntCmpOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1, op2;
@@ -530,7 +559,8 @@
};
/// Integer compare with immediate SVE instruction.
-class SveIntCmpImmOp : public ArmStaticInst {
+class SveIntCmpImmOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -548,7 +578,8 @@
};
/// ADR.
-class SveAdrOp : public ArmStaticInst {
+class SveAdrOp : public ArmStaticInst
+{
public:
enum SveAdrOffsetFormat {
SveAdrOffsetPacked,
@@ -574,7 +605,8 @@
};
/// Element count SVE instruction.
-class SveElemCountOp : public ArmStaticInst {
+class SveElemCountOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
uint8_t pattern;
@@ -595,7 +627,8 @@
};
/// Partition break SVE instruction.
-class SvePartBrkOp : public ArmStaticInst {
+class SvePartBrkOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex gp;
@@ -613,7 +646,8 @@
};
/// Partition break with propagation SVE instruction.
-class SvePartBrkPropOp : public ArmStaticInst {
+class SvePartBrkPropOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -631,7 +665,8 @@
};
/// Scalar element select SVE instruction.
-class SveSelectOp : public ArmStaticInst {
+class SveSelectOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -655,7 +690,8 @@
};
/// SVE unary operation on predicate (predicated)
-class SveUnaryPredPredOp : public ArmStaticInst {
+class SveUnaryPredPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -672,7 +708,8 @@
};
/// SVE table lookup/permute using vector of element indices (TBL)
-class SveTblOp : public ArmStaticInst {
+class SveTblOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -688,7 +725,8 @@
};
/// SVE unpack and widen predicate
-class SveUnpackOp : public ArmStaticInst {
+class SveUnpackOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -703,7 +741,8 @@
};
/// SVE predicate test
-class SvePredTestOp : public ArmStaticInst {
+class SvePredTestOp : public ArmStaticInst
+{
protected:
IntRegIndex op1;
IntRegIndex gp;
@@ -718,7 +757,8 @@
};
/// SVE unary predicate instructions with implicit source operand
-class SvePredUnaryWImplicitSrcOp : public ArmStaticInst {
+class SvePredUnaryWImplicitSrcOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
@@ -732,7 +772,8 @@
};
/// SVE unary predicate instructions, predicated, with implicit source
operand
-class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst {
+class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex gp;
@@ -748,7 +789,8 @@
};
/// SVE unary predicate instructions with implicit destination operand
-class SvePredUnaryWImplicitDstOp : public ArmStaticInst {
+class SvePredUnaryWImplicitDstOp : public ArmStaticInst
+{
protected:
IntRegIndex op1;
@@ -762,7 +804,8 @@
};
/// SVE unary predicate instructions with implicit destination operand
-class SveWImplicitSrcDstOp : public ArmStaticInst {
+class SveWImplicitSrcDstOp : public ArmStaticInst
+{
protected:
SveWImplicitSrcDstOp(const char* mnem, ExtMachInst _machInst,
OpClass __opClass) :
@@ -773,7 +816,8 @@
};
/// SVE vector - immediate binary operation
-class SveBinImmUnpredDestrOp : public ArmStaticInst {
+class SveBinImmUnpredDestrOp : public ArmStaticInst
+{
protected:
IntRegIndex dest;
IntRegIndex op1;
@@ -790,7 +834,8 @@
};
/// Binary with immediate index, destructive, unpredicated SVE instruction.
-class SveBinImmIdxUnpredOp : public ArmStaticInst {
+class SveBinImmIdxUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1;
uint64_t imm;
@@ -807,7 +852,8 @@
};
/// Unary unpredicated scalar to vector instruction
-class SveUnarySca2VecUnpredOp : public ArmStaticInst {
+class SveUnarySca2VecUnpredOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1;
bool simdFp;
@@ -824,7 +870,8 @@
};
/// SVE dot product instruction (indexed)
-class SveDotProdIdxOp : public ArmStaticInst {
+class SveDotProdIdxOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
uint64_t imm;
@@ -843,7 +890,8 @@
};
/// SVE dot product instruction (vectors)
-class SveDotProdOp : public ArmStaticInst {
+class SveDotProdOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
uint8_t esize;
@@ -861,7 +909,8 @@
};
/// SVE Complex Instructions (vectors)
-class SveComplexOp : public ArmStaticInst {
+class SveComplexOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2, gp;
uint8_t rot;
@@ -879,7 +928,8 @@
};
/// SVE Complex Instructions (indexed)
-class SveComplexIdxOp : public ArmStaticInst {
+class SveComplexIdxOp : public ArmStaticInst
+{
protected:
IntRegIndex dest, op1, op2;
uint8_t rot, imm;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c5c330f..57daba5 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -136,7 +136,8 @@
/** Metadata table accessible via the value of the register */
static std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
- class MiscRegLUTEntryInitializer {
+ class MiscRegLUTEntryInitializer
+ {
struct MiscRegLUTEntry &entry;
std::bitset<NUM_MISCREG_INFOS> &info;
typedef const MiscRegLUTEntryInitializer& chain;
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index e8c63bf..f5c8c7e 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -91,7 +91,8 @@
* @see The ARM Architecture Refererence Manual (DDI 0487A)
*
*/
-class PMU : public SimObject, public ArmISA::BaseISADevice {
+class PMU : public SimObject, public ArmISA::BaseISADevice
+{
public:
PMU(const ArmPMUParams &p);
~PMU();
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 047eb3b..b9e2e06 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -63,7 +63,8 @@
public:
class WalkerState;
- class DescriptorBase {
+ class DescriptorBase
+ {
public:
DescriptorBase() : lookupLevel(L0) {}
@@ -89,7 +90,8 @@
}
};
- class L1Descriptor : public DescriptorBase {
+ class L1Descriptor : public DescriptorBase
+ {
public:
/** Type of page table entry ARM DDI 0406B: B3-8*/
enum EntryType {
@@ -240,7 +242,8 @@
};
/** Level 2 page table descriptor */
- class L2Descriptor : public DescriptorBase {
+ class L2Descriptor : public DescriptorBase
+ {
public:
/** The raw bits of the entry. */
uint32_t data;
@@ -372,7 +375,8 @@
};
/** Long-descriptor format (LPAE) */
- class LongDescriptor : public DescriptorBase {
+ class LongDescriptor : public DescriptorBase
+ {
public:
/** Descriptor type */
enum EntryType {
diff --git a/src/base/bitunion.test.cc b/src/base/bitunion.test.cc
index 594193d..ced108b 100644
--- a/src/base/bitunion.test.cc
+++ b/src/base/bitunion.test.cc
@@ -131,7 +131,8 @@
EmptySixteen emptySixteen;
EmptyEight emptyEight(0);
-class BitUnionData : public testing::Test {
+class BitUnionData : public testing::Test
+{
protected:
SixtyFour sixtyFour;
Split split;
diff --git a/src/cpu/o3/fu_pool.hh b/src/cpu/o3/fu_pool.hh
index 4659fe7..45769a1 100644
--- a/src/cpu/o3/fu_pool.hh
+++ b/src/cpu/o3/fu_pool.hh
@@ -89,7 +89,8 @@
* by iterating through it, thus leaving free units at the head of the
* queue.
*/
- class FUIdxQueue {
+ class FUIdxQueue
+ {
public:
/** Constructs a circular queue of FU indices. */
FUIdxQueue()
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 0286a6e..b14ba4d 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -94,7 +94,8 @@
typedef typename std::list<DynInstPtr>::iterator ListIt;
/** FU completion event class. */
- class FUCompletion : public Event {
+ class FUCompletion : public Event
+ {
private:
/** Executing instruction. */
DynInstPtr inst;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index f4c0f8f..8817961 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -173,7 +173,8 @@
* when the instruction is ready to execute and what instructions
depend
* upon it.
*/
- class MemDepEntry {
+ class MemDepEntry
+ {
public:
/** Constructs a memory dependence entry. */
MemDepEntry(const DynInstPtr &new_inst)
diff --git a/src/cpu/o3/probe/simple_trace.hh
b/src/cpu/o3/probe/simple_trace.hh
index 2cd409f..45f85a9 100644
--- a/src/cpu/o3/probe/simple_trace.hh
+++ b/src/cpu/o3/probe/simple_trace.hh
@@ -49,7 +49,8 @@
#include "params/SimpleTrace.hh"
#include "sim/probe/probe.hh"
-class SimpleTrace : public ProbeListenerObject {
+class SimpleTrace : public ProbeListenerObject
+{
public:
SimpleTrace(const SimpleTraceParams ¶ms):
diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh
index 4d2a53e..df63c04 100644
--- a/src/cpu/pc_event.hh
+++ b/src/cpu/pc_event.hh
@@ -71,7 +71,8 @@
class PCEventQueue : public PCEventScope
{
protected:
- class MapCompare {
+ class MapCompare
+ {
public:
bool
operator()(PCEvent * const &l, PCEvent * const &r) const
diff --git a/src/cpu/pred/multiperspective_perceptron.hh
b/src/cpu/pred/multiperspective_perceptron.hh
index 4f5f613..9abff01 100644
--- a/src/cpu/pred/multiperspective_perceptron.hh
+++ b/src/cpu/pred/multiperspective_perceptron.hh
@@ -51,7 +51,8 @@
/**
* Branch information data
*/
- class MPPBranchInfo {
+ class MPPBranchInfo
+ {
/** pc of the branch */
const unsigned int pc;
/** pc of the branch, shifted 2 bits to the right */
@@ -167,7 +168,8 @@
* Local history entries, each enty contains the history of directions
* taken by a given branch.
*/
- class LocalHistories {
+ class LocalHistories
+ {
/** The array of histories */
std::vector<unsigned int> localHistories;
/** Size in bits of each history entry */
@@ -480,7 +482,8 @@
/** Available features */
- class GHIST : public HistorySpec {
+ class GHIST : public HistorySpec
+ {
public:
GHIST(int p1, int p2, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -531,7 +534,8 @@
}
};
- class ACYCLIC : public HistorySpec {
+ class ACYCLIC : public HistorySpec
+ {
public:
ACYCLIC(int p1, int p2, int p3, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -579,7 +583,8 @@
}
};
- class MODHIST : public HistorySpec {
+ class MODHIST : public HistorySpec
+ {
public:
MODHIST(int p1, int p2, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -608,7 +613,8 @@
}
};
- class BIAS : public HistorySpec {
+ class BIAS : public HistorySpec
+ {
public:
BIAS(double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -623,7 +629,8 @@
};
- class RECENCY : public HistorySpec {
+ class RECENCY : public HistorySpec
+ {
public:
RECENCY(int p1, int p2, int p3, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -665,7 +672,8 @@
}
};
- class IMLI : public HistorySpec {
+ class IMLI : public HistorySpec
+ {
public:
IMLI(int p1, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -686,7 +694,8 @@
}
};
- class PATH : public HistorySpec {
+ class PATH : public HistorySpec
+ {
public:
PATH(int p1, int p2, int p3, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -732,7 +741,8 @@
}
};
- class LOCAL : public HistorySpec {
+ class LOCAL : public HistorySpec
+ {
public:
LOCAL(int p1, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -754,7 +764,8 @@
}
};
- class MODPATH : public HistorySpec {
+ class MODPATH : public HistorySpec
+ {
public:
MODPATH(int p1, int p2, int p3, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -781,7 +792,8 @@
}
};
- class GHISTPATH : public HistorySpec {
+ class GHISTPATH : public HistorySpec
+ {
public:
GHISTPATH(int p1, int p2, int p3, double coeff, int size, int
width,
MultiperspectivePerceptron &mpp)
@@ -853,7 +865,8 @@
}
};
- class GHISTMODPATH : public HistorySpec {
+ class GHISTMODPATH : public HistorySpec
+ {
public:
GHISTMODPATH(int p1, int p2, int p3, double coeff, int size, int
width,
MultiperspectivePerceptron &mpp)
@@ -885,7 +898,8 @@
}
};
- class BLURRYPATH : public HistorySpec {
+ class BLURRYPATH : public HistorySpec
+ {
public:
BLURRYPATH(int p1, int p2, int p3, double coeff, int size, int
width,
MultiperspectivePerceptron &mpp)
@@ -931,7 +945,8 @@
}
};
- class RECENCYPOS : public HistorySpec {
+ class RECENCYPOS : public HistorySpec
+ {
public:
RECENCYPOS(int p1, double coeff, int size, int width,
MultiperspectivePerceptron &mpp)
@@ -972,7 +987,8 @@
}
};
- class SGHISTPATH : public HistorySpec {
+ class SGHISTPATH : public HistorySpec
+ {
public:
SGHISTPATH(int p1, int p2, int p3, double coeff, int size, int
width,
MultiperspectivePerceptron &mpp)
diff --git a/src/cpu/pred/multiperspective_perceptron_64KB.hh
b/src/cpu/pred/multiperspective_perceptron_64KB.hh
index 7ab932c..4d24e86 100644
--- a/src/cpu/pred/multiperspective_perceptron_64KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_64KB.hh
@@ -43,7 +43,8 @@
#include "cpu/pred/multiperspective_perceptron.hh"
#include "params/MultiperspectivePerceptron64KB.hh"
-class MultiperspectivePerceptron64KB : public MultiperspectivePerceptron {
+class MultiperspectivePerceptron64KB : public MultiperspectivePerceptron
+{
void createSpecs() override;
public:
MultiperspectivePerceptron64KB(
diff --git a/src/cpu/pred/multiperspective_perceptron_8KB.hh
b/src/cpu/pred/multiperspective_perceptron_8KB.hh
index e297dfc..d02baf9 100644
--- a/src/cpu/pred/multiperspective_perceptron_8KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_8KB.hh
@@ -43,7 +43,8 @@
#include "cpu/pred/multiperspective_perceptron.hh"
#include "params/MultiperspectivePerceptron8KB.hh"
-class MultiperspectivePerceptron8KB : public MultiperspectivePerceptron {
+class MultiperspectivePerceptron8KB : public MultiperspectivePerceptron
+{
void createSpecs() override;
public:
MultiperspectivePerceptron8KB(
diff --git a/src/cpu/pred/multiperspective_perceptron_tage.hh
b/src/cpu/pred/multiperspective_perceptron_tage.hh
index fb9d94f..44519a5 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage.hh
@@ -48,7 +48,8 @@
#include "params/MPP_TAGE.hh"
#include "params/MultiperspectivePerceptronTAGE.hh"
-class MPP_TAGE : public TAGEBase {
+class MPP_TAGE : public TAGEBase
+{
std::vector<unsigned int> tunedHistoryLengths;
public:
struct BranchInfo : public TAGEBase::BranchInfo {
@@ -82,7 +83,8 @@
bool taken, Addr branch_pc, Addr
target);
};
-class MPP_LoopPredictor : public LoopPredictor {
+class MPP_LoopPredictor : public LoopPredictor
+{
public:
MPP_LoopPredictor(const MPP_LoopPredictorParams &p) : LoopPredictor(p)
{}
@@ -91,7 +93,8 @@
bool optionalAgeInc() const override;
};
-class MPP_StatisticalCorrector : public StatisticalCorrector {
+class MPP_StatisticalCorrector : public StatisticalCorrector
+{
protected:
int8_t thirdH;
// global branch history variation GEHL
diff --git a/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
b/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
index ba94631..4336bac 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
@@ -43,7 +43,8 @@
#include "params/MPP_StatisticalCorrector_64KB.hh"
#include "params/MultiperspectivePerceptronTAGE64KB.hh"
-class MPP_StatisticalCorrector_64KB : public MPP_StatisticalCorrector {
+class MPP_StatisticalCorrector_64KB : public MPP_StatisticalCorrector
+{
const unsigned numEntriesSecondLocalHistories;
const unsigned numEntriesThirdLocalHistories;
diff --git a/src/cpu/pred/tage_sc_l.hh b/src/cpu/pred/tage_sc_l.hh
index d4986e2..6b98489 100644
--- a/src/cpu/pred/tage_sc_l.hh
+++ b/src/cpu/pred/tage_sc_l.hh
@@ -49,7 +49,8 @@
#include "params/TAGE_SC_L_LoopPredictor.hh"
#include "params/TAGE_SC_L_TAGE.hh"
-class TAGE_SC_L_TAGE : public TAGEBase {
+class TAGE_SC_L_TAGE : public TAGEBase
+{
const unsigned firstLongTagTable;
const unsigned longTagsSize;
const unsigned shortTagsSize;
diff --git a/src/cpu/pred/tage_sc_l_64KB.hh b/src/cpu/pred/tage_sc_l_64KB.hh
index 01f5e38..87b49be 100644
--- a/src/cpu/pred/tage_sc_l_64KB.hh
+++ b/src/cpu/pred/tage_sc_l_64KB.hh
@@ -50,7 +50,8 @@
#include "params/TAGE_SC_L_64KB_StatisticalCorrector.hh"
#include "params/TAGE_SC_L_TAGE_64KB.hh"
-class TAGE_SC_L_TAGE_64KB : public TAGE_SC_L_TAGE {
+class TAGE_SC_L_TAGE_64KB : public TAGE_SC_L_TAGE
+{
public:
TAGE_SC_L_TAGE_64KB(const TAGE_SC_L_TAGE_64KBParams &p) :
TAGE_SC_L_TAGE(p)
{}
diff --git a/src/cpu/testers/gpu_ruby_test/episode.hh
b/src/cpu/testers/gpu_ruby_test/episode.hh
index e10025e..5b181e5 100644
--- a/src/cpu/testers/gpu_ruby_test/episode.hh
+++ b/src/cpu/testers/gpu_ruby_test/episode.hh
@@ -47,7 +47,8 @@
typedef AddressManager::Location Location;
typedef AddressManager::Value Value;
- class Action {
+ class Action
+ {
public:
enum class Type {
ACQUIRE,
diff --git a/src/dev/hsa/hsa_driver.hh b/src/dev/hsa/hsa_driver.hh
index d4af0f1..13119a5 100644
--- a/src/dev/hsa/hsa_driver.hh
+++ b/src/dev/hsa/hsa_driver.hh
@@ -79,7 +79,8 @@
HSADriver *driver;
ThreadContext *tc;
};
- class EventTableEntry {
+ class EventTableEntry
+ {
public:
EventTableEntry() :
mailBoxPtr(0), tc(nullptr), threadWaiting(false),
setEvent(false)
@@ -118,7 +119,8 @@
// reset all events when one of those events wake up this thread. The
// signal events that can wake up this thread are stored in
signalEvents
// whereas the timer wakeup event is stored in timerEvent.
- class EventList {
+ class EventList
+ {
public:
EventList() : driver(nullptr), timerEvent(nullptr, nullptr) {}
EventList(HSADriver *hsa_driver, ThreadContext *thrd_cntxt)
diff --git a/src/dev/hsa/hsa_packet_processor.hh
b/src/dev/hsa/hsa_packet_processor.hh
index e79ffb1..fc8f579 100644
--- a/src/dev/hsa/hsa_packet_processor.hh
+++ b/src/dev/hsa/hsa_packet_processor.hh
@@ -69,7 +69,8 @@
class HWScheduler;
// Our internal representation of an HSA queue
-class HSAQueueDescriptor {
+class HSAQueueDescriptor
+{
public:
uint64_t basePointer;
uint64_t doorbellPointer;
diff --git a/src/dev/riscv/clint.hh b/src/dev/riscv/clint.hh
index 1f213ce..05fdc4e 100644
--- a/src/dev/riscv/clint.hh
+++ b/src/dev/riscv/clint.hh
@@ -100,8 +100,8 @@
* ...: reserved[1]
* 0xBFF8: mtime (read-only)
*/
- class ClintRegisters: public RegisterBankLE {
-
+ class ClintRegisters: public RegisterBankLE
+ {
public:
const Addr mtimecmpStart = 0x4000;
const Addr mtimeStart = 0xBFF8;
diff --git a/src/dev/riscv/hifive.hh b/src/dev/riscv/hifive.hh
index e4d162e..afa65c1 100644
--- a/src/dev/riscv/hifive.hh
+++ b/src/dev/riscv/hifive.hh
@@ -44,7 +44,9 @@
#include "params/HiFive.hh"
using namespace RiscvISA;
-class HiFive : public Platform {
+
+class HiFive : public Platform
+{
public:
System *system;
Clint *clint;
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index a0dfbbf..e40031a 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -182,7 +182,8 @@
*
* ... reserved[3]
*/
- class PlicRegisters: public RegisterBankLE {
+ class PlicRegisters: public RegisterBankLE
+ {
public:
const Addr pendingStart = 0x1000;
const Addr enableStart = 0x2000;
diff --git a/src/dev/storage/ide_disk.hh b/src/dev/storage/ide_disk.hh
index a0e02ce..f93f4b6 100644
--- a/src/dev/storage/ide_disk.hh
+++ b/src/dev/storage/ide_disk.hh
@@ -72,7 +72,8 @@
uint16_t endOfTable;
} PrdEntry_t;
-class PrdTableEntry {
+class PrdTableEntry
+{
public:
PrdEntry_t entry;
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index 72ad02e..6e099fc 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -292,8 +292,9 @@
* @note Queues must be registered with
* VirtIODeviceBase::registerQueue() to be active.
*/
-class VirtQueue : public Serializable {
-public:
+class VirtQueue : public Serializable
+{
+ public:
virtual ~VirtQueue() {};
/** @{
diff --git a/src/kern/operatingsystem.hh b/src/kern/operatingsystem.hh
index 8dd6c05..021c6ce 100644
--- a/src/kern/operatingsystem.hh
+++ b/src/kern/operatingsystem.hh
@@ -49,7 +49,8 @@
/// functions, and syscall-number mappings specific to an operating system
/// syscall interface.
///
-class OperatingSystem {
+class OperatingSystem
+{
public:
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 2b36a86..9b30240 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -59,7 +59,8 @@
* Locked address class that represents a physical address and a
* context id.
*/
-class LockedAddr {
+class LockedAddr
+{
private:
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 8951a5e..0d676f2 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1362,7 +1362,8 @@
* line) we switch to NO_ALLOCATE when writes should not allocate in
* the cache but rather send a whole line write to the memory below.
*/
-class WriteAllocator : public SimObject {
+class WriteAllocator : public SimObject
+{
public:
WriteAllocator(const WriteAllocatorParams &p) :
SimObject(p),
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index b1038c8..ac2878a 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -110,7 +110,8 @@
* Represents that the indicated thread context has a "lock" on
* the block, in the LL/SC sense.
*/
- class Lock {
+ class Lock
+ {
public:
ContextID contextId; // locking context
Addr lowAddr; // low address of lock range
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index e1529ce..7311dfa 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -121,7 +121,8 @@
/** True if the entry is just a simple forward from an upper level */
bool isForward;
- class Target : public QueueEntry::Target {
+ class Target : public QueueEntry::Target
+ {
public:
enum Source {
@@ -159,7 +160,8 @@
{}
};
- class TargetList : public std::list<Target> {
+ class TargetList : public std::list<Target>
+ {
public:
bool needsWritable;
diff --git a/src/mem/cache/prefetch/associative_set.hh
b/src/mem/cache/prefetch/associative_set.hh
index 9fc7b98..61fd1f6 100644
--- a/src/mem/cache/prefetch/associative_set.hh
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -39,7 +39,8 @@
* bool value is used as an additional tag data of the entry.
*/
template<class Entry>
-class AssociativeSet {
+class AssociativeSet
+{
static_assert(std::is_base_of<TaggedEntry, Entry>::value,
"Entry must derive from TaggedEntry");
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 2dcc95f..af1ad1a 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -87,7 +87,8 @@
* Class containing the information needed by the prefetch to train and
* generate new prefetch requests.
*/
- class PrefetchInfo {
+ class PrefetchInfo
+ {
/** The address used to train and generate prefetches */
Addr address;
/** The program counter that generated this address. */
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 8159563..48d17c7 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -80,7 +80,8 @@
* stored in a target containing its availability, order and other
info,
* and the queue entry stores these similar targets in a list.
*/
- class Target {
+ class Target
+ {
public:
const Tick recvTime; //!< Time when request was received (for
stats)
const Tick readyTime; //!< Time when request is ready to be
serviced
diff --git a/src/mem/cache/write_queue_entry.hh
b/src/mem/cache/write_queue_entry.hh
index 2aebacf..d50de35 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -73,7 +73,8 @@
friend class WriteQueue;
public:
- class TargetList : public std::list<Target> {
+ class TargetList : public std::list<Target>
+ {
public:
diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh
index baf6152..1509862 100644
--- a/src/mem/packet_queue.hh
+++ b/src/mem/packet_queue.hh
@@ -63,7 +63,8 @@
{
private:
/** A deferred packet, buffered to transmit later. */
- class DeferredPacket {
+ class DeferredPacket
+ {
public:
Tick tick; ///< The tick when the packet is ready to transmit
PacketPtr pkt; ///< Pointer to the packet to transmit
diff --git a/src/mem/ruby/structures/TBEStorage.hh
b/src/mem/ruby/structures/TBEStorage.hh
index 1a65907..358fa0c 100644
--- a/src/mem/ruby/structures/TBEStorage.hh
+++ b/src/mem/ruby/structures/TBEStorage.hh
@@ -70,7 +70,8 @@
// the current TBETable would be cumbersome since the TBETable is indexed
// by the transaction address.
-class TBEStorage {
+class TBEStorage
+{
public:
TBEStorage(Stats::Group *parent, int number_of_TBEs);
diff --git a/src/mem/ruby/system/CacheRecorder.hh
b/src/mem/ruby/system/CacheRecorder.hh
index 53ab8e5..b295be6 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -51,7 +51,8 @@
* length object, so that while writing the data to a file one does not
* need to copy the meta data and the actual data separately.
*/
-class TraceRecord {
+class TraceRecord
+{
public:
int m_cntrl_id;
Tick m_time;
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index abd66a8..42f95ca 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -83,7 +83,8 @@
* (4) ordering: there is no single point of order in the system. Instead,
* requesting MSHRs track order between local requests and remote
snoops
*/
-class SnoopFilter : public SimObject {
+class SnoopFilter : public SimObject
+{
public:
// Change for systems with more than 256 ports tracked by this object
diff --git a/src/sim/futex_map.hh b/src/sim/futex_map.hh
index 081b850..a8a8141 100644
--- a/src/sim/futex_map.hh
+++ b/src/sim/futex_map.hh
@@ -38,7 +38,8 @@
* FutexKey class defines an unique identifier for a particular futex in
the
* system. The tgid and an address are the unique values needed as the key.
*/
-class FutexKey {
+class FutexKey
+{
public:
uint64_t addr;
uint64_t tgid;
@@ -65,7 +66,8 @@
* WaiterState defines internal state of a waiter thread. The state
* includes a pointer to the thread's context and its associated bitmask.
*/
-class WaiterState {
+class WaiterState
+{
public:
ThreadContext* tc;
int bitmask;
diff --git a/src/sim/linear_solver.hh b/src/sim/linear_solver.hh
index ca59a81..0ecf7f7 100644
--- a/src/sim/linear_solver.hh
+++ b/src/sim/linear_solver.hh
@@ -49,7 +49,8 @@
* N+1 coefficients.
*/
-class LinearEquation {
+class LinearEquation
+{
public:
LinearEquation(unsigned unknowns) {
eq = std::vector <double> (unknowns + 1, 0);
@@ -104,7 +105,8 @@
std::vector <double> eq;
};
-class LinearSystem {
+class LinearSystem
+{
public:
LinearSystem(unsigned unknowns) {
for (unsigned i = 0; i < unknowns; i++)
diff --git a/src/sim/mathexpr.hh b/src/sim/mathexpr.hh
index 3dfe2b8..73247c2 100644
--- a/src/sim/mathexpr.hh
+++ b/src/sim/mathexpr.hh
@@ -44,7 +44,8 @@
#include <string>
#include <vector>
-class MathExpr {
+class MathExpr
+{
public:
MathExpr(std::string expr);
@@ -102,7 +103,8 @@
/** Operator list */
std::array<OpSearch, uNeg + 1> ops;
- class Node {
+ class Node
+ {
public:
Node() : op(nInvalid), l(0), r(0), value(0) {}
std::string toStr() const {
diff --git a/src/sim/se_signal.hh b/src/sim/se_signal.hh
index e3241f5..f5f1675 100644
--- a/src/sim/se_signal.hh
+++ b/src/sim/se_signal.hh
@@ -33,7 +33,8 @@
class Process;
-class BasicSignal {
+class BasicSignal
+{
public:
Process *sender;
Process *receiver;
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 82bfd2e..25a6e8d 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -169,7 +169,8 @@
class Serializable
{
public:
- class ScopedCheckpointSection {
+ class ScopedCheckpointSection
+ {
public:
/**
* This is the constructor for Scoped checkpoint section helper
diff --git a/src/sim/syscall_desc.hh b/src/sim/syscall_desc.hh
index 2fd2434..cee0f0c 100644
--- a/src/sim/syscall_desc.hh
+++ b/src/sim/syscall_desc.hh
@@ -63,7 +63,8 @@
* bound to the ISAs in the architecture specific code
* (i.e. arch/X86/linux/process.cc).
*/
-class SyscallDesc {
+class SyscallDesc
+{
public:
/**
* Interface for invoking the system call funcion pointer. Note that
diff --git a/src/sim/syscall_emul_buf.hh b/src/sim/syscall_emul_buf.hh
index dbe9f96..2a79ccd 100644
--- a/src/sim/syscall_emul_buf.hh
+++ b/src/sim/syscall_emul_buf.hh
@@ -51,7 +51,8 @@
* and copyOut() methods copy the user-space buffer to and from the
* simulator-space buffer, respectively.
*/
-class BaseBufferArg {
+class BaseBufferArg
+{
public:
diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
index 49f2d7e..7e80669 100644
--- a/src/unittest/stattest.cc
+++ b/src/unittest/stattest.cc
@@ -63,7 +63,8 @@
return 9.8;
}
-class TestClass {
+class TestClass
+{
public:
double operator()() { return 9.7; }
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39015
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Gerrit-Change-Number: 39015
Gerrit-PatchSet: 4
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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