Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40178 )
Change subject: arch: Eliminate the GuestByteOrder constant.
......................................................................
arch: Eliminate the GuestByteOrder constant.
Most ISAs used that constant exactly once, when setting up a Process.
This change just propogates the constant to the one place it's used. In
MIPS, the endianness is hard coded as little. There were some checks
which would change the behavior if the endianness was big. This change
removes that dead code. If someone wants to add support for big endian
MIPS, they can go back and add in the small bits of code that would be
required. It's likely the existing big endian support was incomplete and
not tested, so it's probably best for someone interested in it to start
fresh anyway.
Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40178
Tested-by: kokoro <[email protected]>
Reviewed-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Daniel Carvalho <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/isa_traits.hh
M src/arch/arm/process.cc
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/mem.isa
M src/arch/mips/isa_traits.hh
M src/arch/mips/process.cc
M src/arch/power/isa_traits.hh
M src/arch/power/process.cc
M src/arch/riscv/isa_traits.hh
M src/arch/riscv/process.cc
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/process.cc
M src/arch/x86/isa_traits.hh
M src/arch/x86/process.cc
14 files changed, 11 insertions(+), 32 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 83d35aa..6c858cc 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -43,12 +43,9 @@
#define __ARCH_ARM_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace ArmISA
{
- const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
} // namespace ArmISA
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 91df4c9..0bfbda1 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -429,7 +429,7 @@
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxillary vector
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index e5613f5..ea2b43a 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1532,10 +1532,7 @@
if (Rs<2:0> == 0) {
Fd_ud = Fs_ud;
} else if (Rs<2:0> == 4) {
- if (GuestByteOrder == ByteOrder::big)
- Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
- else
- Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
+ Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
} else {
Fd_ud = Fd_ud;
}
diff --git a/src/arch/mips/isa/formats/mem.isa
b/src/arch/mips/isa/formats/mem.isa
index ac56803..267d5e8 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -498,8 +498,6 @@
uint32_t mem_word = Mem_uw;
uint32_t unalign_addr = Rs + disp;
uint32_t byte_offset = unalign_addr & 3;
- if (GuestByteOrder == ByteOrder::big)
- byte_offset ^= 3;
'''
memacc_code = decl_code + memacc_code
@@ -516,8 +514,6 @@
uint32_t mem_word = 0;
uint32_t unaligned_addr = Rs + disp;
uint32_t byte_offset = unaligned_addr & 3;
- if (GuestByteOrder == ByteOrder::big)
- byte_offset ^= 3;
fault = readMemAtomicLE(xc, traceData, EA, mem_word,
memAccessFlags);
'''
memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index fc87530..541ed63 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -31,13 +31,10 @@
#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace MipsISA
{
-const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 13;
const Addr PageBytes = 1ULL << PageShift;
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index e2f2bb9..0439d09 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -37,6 +37,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
@@ -184,7 +185,7 @@
// Copy the aux vector
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 2466091..e6e7a67 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -32,13 +32,10 @@
#define __ARCH_POWER_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace PowerISA
{
-const ByteOrder GuestByteOrder = ByteOrder::big;
-
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 26d28a8..5cdd299 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -39,6 +39,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
@@ -251,7 +252,7 @@
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxilliary vector
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 58fdbe9..d07ffa2 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -43,13 +43,10 @@
#define __ARCH_RISCV_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace RiscvISA
{
-const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 6718b05..edfbf4b 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -198,7 +198,7 @@
Addr sp = memState->getStackMin();
const auto pushOntoStack =
[this, &sp](IntType data) {
- initVirtMem->write(sp, data, GuestByteOrder);
+ initVirtMem->write(sp, data, ByteOrder::little);
sp += sizeof(data);
};
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index ca96b3b..895b7d5 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -30,13 +30,10 @@
#define __ARCH_SPARC_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace SparcISA
{
-const ByteOrder GuestByteOrder = ByteOrder::big;
-
const Addr PageShift = 13;
const Addr PageBytes = 1ULL << PageShift;
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 191cbf2..e40cb06 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -42,6 +42,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
@@ -326,7 +327,7 @@
// Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
auxv_array_end += sizeof(aux);
}
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index b959ef3..d1dd392 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -39,12 +39,9 @@
#define __ARCH_X86_ISATRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace X86ISA
{
- const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
}
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 20c78ba..2b25fb2 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -60,6 +60,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
#include "sim/syscall_return.hh"
@@ -961,7 +962,7 @@
// Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
// Write out the terminating zeroed auxiliary vector
13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40178
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
Gerrit-Change-Number: 40178
Gerrit-PatchSet: 15
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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