Peter Yuen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/43625 )

Change subject: arch-riscv: Added flexibility to RISC-V FS config
......................................................................

arch-riscv: Added flexibility to RISC-V FS config

Made some small changes to add flexibility to linux boot options.
Also briefly explained the usage in comments.

Change-Id: I4f02e7ffeca3e104a4d640db4cc900a208b74a5a
---
M configs/common/Options.py
M configs/example/riscv/fs_linux.py
2 files changed, 67 insertions(+), 36 deletions(-)



diff --git a/configs/common/Options.py b/configs/common/Options.py
index c48bfe6..1b320c6 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -462,6 +462,12 @@
parser.add_option("--vio-9p", action="store_true", help=vio_9p_help)
         parser.add_option("--bootloader", action='append',
                 help="executable file that runs before the --kernel")
+    if buildEnv['TARGET_ISA'] == "riscv":
+        parser.add_option("--bare-metal", action="store_true",
+            help="Provide the raw system without the linux specific bits")
+        parser.add_option("--dtb-filename", action="store", type="string",
+ help="Specifies device tree blob file to use with device-tree-"\
+              "enabled kernels")

     # Benchmark options
     parser.add_option("--dual", action="store_true",
diff --git a/configs/example/riscv/fs_linux.py b/configs/example/riscv/fs_linux.py
index 28e6714..64ba142 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -1,4 +1,3 @@
-# Copyright (c) 2021 Huawei International
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -10,6 +9,7 @@
 # unmodified and in its entirety in all distributions of the software,
 # modified or unmodified, in source code or in binary form.
 #
+# Copyright (c) 2021 Huawei International
 # Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
 # Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
@@ -63,6 +63,30 @@
 from common.Caches import *
 from common import Options

+# ------------------------- Usage Instructions ------------------------- #
+# Common system confirguration options (cpu types, num cpus, checkpointing
+# etc.) should be supported
+#
+# Ruby not supported in this config file. Not tested on RISC-V FS Linux (as
+# of 25 March 2021).
+#
+# Options (Full System):
+# --kernel (required):          Bootloader + kernel binary (e.g. bbl with
+#                               linux kernel payload)
+# --disk-image (optional): Path to disk image file. Not needed if using
+#                               ramfs (might run into issues though).
+# --command-line (optional):    Specify to override default.
+# --dtb-filename (optional):    Path to DTB file. Auto-generated if empty.
+# --bare-metal (boolean): Use baremetal Riscv (default False). Use this
+#                               if bbl is built with "--with-dts" option.
+# (do not forget to include bootargs in dts file)
+#
+# Not Used:
+# --command-line-file, --script, --frame-capture, --os-type, --timesync,
+# --dual, -b, --etherdump, --root-device, --ruby
+
+
+# ----------------------- DTB Generation Function ---------------------- #

 def generateMemNode(state, mem_range):
     node = FdtNode("memory@%x" % int(mem_range.start))
@@ -73,10 +97,6 @@
     return node

 def generateDtb(system):
-    """
-    Autogenerate DTB. Arguments are the folder where the DTB
-    will be stored, and the name of the DTB file.
-    """
     state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
     root = FdtNode('/')
     root.append(state.addrCellsProperty())
@@ -105,10 +125,6 @@
 Options.addCommonOptions(parser)
 Options.addFSOptions(parser)

-# NOTE: Ruby in FS Linux has not been tested yet
-if '--ruby' in sys.argv:
-    Ruby.define_options(parser)
-
 # ---------------------------- Parse Options --------------------------- #
 (options, args) = parser.parse_args()

@@ -123,14 +139,19 @@
 np = options.num_cpus

 # ---------------------------- Setup System ---------------------------- #
-# Edit this section to customize peripherals and system settings
+# Default Setup
 system = System()
 mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
                         mem=options.mem_size, os_type=options.os_type)
 system.mem_mode = mem_mode
 system.mem_ranges = [AddrRange(start=0x80000000, size=mdesc.mem())]

-system.workload = RiscvLinux()
+if options.bare_metal:
+    system.workload = RiscvBareMetal()
+    system.workload.bootloader = options.kernel
+else:
+    system.workload = RiscvLinux()
+    system.workload.object_file = options.kernel

 system.iobus = IOXBar()
 system.membus = MemBus()
@@ -139,7 +160,7 @@

 system.intrctrl = IntrControl()

-# HiFive platform
+# HiFive Platform
 system.platform = HiFive()

 # RTCCLK (Set to 100MHz for faster simulation)
@@ -147,14 +168,15 @@
 system.platform.clint.int_pin = system.platform.rtc.int_pin

 # VirtIOMMIO
-image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
-image.child.image_file = mdesc.disks()[0]
-system.platform.disk = MmioVirtIO(
-    vio=VirtIOBlock(image=image),
-    interrupt_id=0x8,
-    pio_size=4096,
-    pio_addr=0x10008000
-)
+if options.disk_image:
+ image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
+    image.child.image_file = mdesc.disks()[0]
+    system.platform.disk = MmioVirtIO(
+        vio=VirtIOBlock(image=image),
+        interrupt_id=0x8,
+        pio_size=4096,
+        pio_addr=0x10008000
+    )

 system.bridge = Bridge(delay='50ns')
 system.bridge.mem_side_port = system.iobus.cpu_side_ports
@@ -185,12 +207,6 @@
                                             voltage_domain =
                                             system.cpu_voltage_domain)

-system.workload.object_file = options.kernel
-
-# NOTE: Not yet tested
-if options.script is not None:
-    system.readfile = options.script
-
 system.init_param = options.init_param

 system.cpu = [CPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
@@ -244,18 +260,27 @@

 # --------------------------- DTB Generation --------------------------- #

-generateDtb(system)
-system.workload.dtb_filename = path.join(m5.options.outdir, 'device.dtb')
-# Default DTB address if bbl is bulit with --with-dts option
-system.workload.dtb_addr = 0x87e00000
+if not options.bare_metal:
+    if options.dtb_filename:
+        system.workload.dtb_filename = options.dtb_filename
+    else:
+        generateDtb(system)
+        system.workload.dtb_filename = path.join(
+            m5.options.outdir, 'device.dtb')
+
+    # Default DTB address if bbl is bulit with --with-dts option
+    system.workload.dtb_addr = 0x87e00000

 # Linux boot command flags
-kernel_cmd = [
-    "console=ttyS0",
-    "root=/dev/vda",
-    "ro"
-]
-system.workload.command_line = " ".join(kernel_cmd)
+    if options.command_line:
+        system.workload.command_line = options.command_line
+    else:
+        kernel_cmd = [
+            "console=ttyS0",
+            "root=/dev/vda",
+            "ro"
+        ]
+        system.workload.command_line = " ".join(kernel_cmd)

 # ---------------------------- Default Setup --------------------------- #


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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: I4f02e7ffeca3e104a4d640db4cc900a208b74a5a
Gerrit-Change-Number: 43625
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen <petery....@huawei.com>
Gerrit-MessageType: newchange
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