Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43347 )
Change subject: dev,cpu,configs: Get rid of the IntrControl device.
......................................................................
dev,cpu,configs: Get rid of the IntrControl device.
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.
Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M configs/common/FSConfig.py
M configs/example/arm/devices.py
M configs/example/riscv/fs_linux.py
D src/cpu/IntrControl.py
M src/cpu/SConscript
D src/cpu/intr_control.cc
D src/cpu/intr_control.hh
D src/cpu/intr_control_noisa.cc
M src/dev/Platform.py
M src/dev/arm/RealView.py
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v2m.hh
M src/dev/arm/gic_v3.cc
M src/dev/arm/realview.cc
M src/dev/arm/realview.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
M src/dev/mips/Malta.py
M src/dev/mips/malta.cc
M src/dev/mips/malta.hh
M src/dev/mips/malta_cchip.cc
M src/dev/platform.cc
M src/dev/platform.hh
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/clint.cc
M src/dev/riscv/clint.hh
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
M src/dev/sparc/T1000.py
M src/dev/sparc/iob.cc
M src/dev/sparc/iob.hh
M src/dev/sparc/t1000.cc
M src/dev/sparc/t1000.hh
M src/dev/storage/ide_ctrl.cc
M src/dev/x86/pc.cc
M src/dev/x86/pc.hh
M tests/gem5/x86-boot-tests/system/system.py
42 files changed, 88 insertions(+), 370 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6665225..22b1ee1 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -122,7 +122,6 @@
AddrRange(Addr('2GB'), size ='256MB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
- self.intrctrl = IntrControl()
self.disk0 = CowMmDisk()
self.disk0.childImage(mdesc.disks()[0])
self.disk0.pio = self.iobus.master
@@ -332,7 +331,6 @@
dev, self.iobus,
dma_ports=self._dma_ports if ruby else None)
- self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
@@ -379,7 +377,6 @@
self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(
image_file = mdesc.disks()[0], read_only = True))
- self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.terminal = Terminal()
self.console = binary('mips/console')
@@ -488,8 +485,6 @@
else:
connectX86ClassicSystem(self, numCPUs)
- self.intrctrl = IntrControl()
-
# Disks
disks = makeCowDisks(mdesc.disks())
self.pc.south_bridge.ide.disks = disks
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 6574eef..0ab2ecd 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -296,7 +296,6 @@
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
- self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 28e6714..3c781ac 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -137,8 +137,6 @@
system.system_port = system.membus.cpu_side_ports
-system.intrctrl = IntrControl()
-
# HiFive platform
system.platform = HiFive()
diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py
deleted file mode 100644
index d38f8d1..0000000
--- a/src/cpu/IntrControl.py
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class IntrControl(SimObject):
- type = 'IntrControl'
- cxx_header = "cpu/intr_control.hh"
- sys = Param.System(Parent.any, "the system we are part of")
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 24c2d67..41af2bf 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -64,7 +64,6 @@
DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
DebugFlag('Fetch')
DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
-DebugFlag('IntrControl')
DebugFlag('O3PipeView')
DebugFlag('PCEvent')
DebugFlag('Quiesce')
@@ -83,8 +82,6 @@
Source('pc_event.cc')
if env['TARGET_ISA'] == 'null':
- SimObject('IntrControl.py')
- Source('intr_control_noisa.cc')
Return()
# Only build the protocol buffer instructions tracer if we have protobuf
support
@@ -97,7 +94,6 @@
SimObject('BaseCPU.py')
SimObject('CPUTracers.py')
SimObject('FuncUnit.py')
-SimObject('IntrControl.py')
SimObject('TimingExpr.py')
Source('activity.cc')
@@ -105,7 +101,6 @@
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
-Source('intr_control.cc')
Source('nativetrace.cc')
Source('profile.cc')
Source('reg_class.cc')
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
deleted file mode 100644
index 74e0457..0000000
--- a/src/cpu/intr_control.cc
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "cpu/intr_control.hh"
-
-#include <string>
-#include <vector>
-
-#include "base/trace.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "debug/IntrControl.hh"
-#include "sim/sim_object.hh"
-
-IntrControl::IntrControl(const Params &p)
- : SimObject(p), sys(p.sys)
-{}
-
-void
-IntrControl::post(int cpu_id, int int_num, int index)
-{
- DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
- auto *tc = sys->threads[cpu_id];
- tc->getCpuPtr()->postInterrupt(tc->threadId(), int_num, index);
-}
-
-void
-IntrControl::clear(int cpu_id, int int_num, int index)
-{
- DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
- auto *tc = sys->threads[cpu_id];
- tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_num, index);
-}
-
-void
-IntrControl::clearAll(int cpu_id)
-{
- DPRINTF(IntrControl, "Clear all pending interrupts for CPU %d\n",
cpu_id);
- auto *tc = sys->threads[cpu_id];
- tc->getCpuPtr()->clearInterrupts(tc->threadId());
-}
-
-bool
-IntrControl::havePosted(int cpu_id) const
-{
- DPRINTF(IntrControl, "Check pending interrupts for CPU %d\n", cpu_id);
- auto *tc = sys->threads[cpu_id];
- return tc->getCpuPtr()->checkInterrupts(tc->threadId());
-}
diff --git a/src/cpu/intr_control.hh b/src/cpu/intr_control.hh
deleted file mode 100644
index fcb406c..0000000
--- a/src/cpu/intr_control.hh
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __INTR_CONTROL_HH__
-#define __INTR_CONTROL_HH__
-
-#include <vector>
-
-#include "base/logging.hh"
-#include "params/IntrControl.hh"
-#include "sim/sim_object.hh"
-#include "sim/system.hh"
-
-class IntrControl : public SimObject
-{
- public:
- System *sys;
- typedef IntrControlParams Params;
- IntrControl(const Params &p);
-
- void clear(int cpu_id, int int_num, int index);
- void post(int cpu_id, int int_num, int index);
- void clearAll(int cpu_id);
- bool havePosted(int cpu_id) const;
-
- void
- clear(int int_num, int index = 0)
- {
- clear(0, int_num, index);
- }
-
- void
- post(int int_num, int index = 0)
- {
- post(0, int_num, index);
- }
-};
-
-#endif // __INTR_CONTROL_HH__
-
-
-
-
-
-
-
diff --git a/src/cpu/intr_control_noisa.cc b/src/cpu/intr_control_noisa.cc
deleted file mode 100644
index 71d2c02..0000000
--- a/src/cpu/intr_control_noisa.cc
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "cpu/intr_control.hh"
-
-IntrControl::IntrControl(const Params &p)
- : SimObject(p), sys(p.sys)
-{}
-
-void
-IntrControl::post(int cpu_id, int int_num, int index)
-{
-}
-
-void
-IntrControl::clear(int cpu_id, int int_num, int index)
-{
-}
diff --git a/src/dev/Platform.py b/src/dev/Platform.py
index 2048fe3..fdc661e 100644
--- a/src/dev/Platform.py
+++ b/src/dev/Platform.py
@@ -32,7 +32,7 @@
type = 'Platform'
abstract = True
cxx_header = "dev/platform.hh"
- intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+ system = Param.System(Parent.any, "system")
# for platforms using device trees to set properties of CPU nodes
def annotateCpuDeviceNode(self, cpu, state):
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index e3558e3..a7080d8 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -649,7 +649,6 @@
class RealView(Platform):
type = 'RealView'
cxx_header = "dev/arm/realview.hh"
- system = Param.System(Parent.any, "system")
_mem_regions = [ AddrRange(0, size='256MiB') ]
_num_pci_dev = 0
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 1d284c1..df4969d 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -41,6 +41,7 @@
#include "dev/arm/gic_v2.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/GIC.hh"
#include "debug/IPI.hh"
@@ -917,10 +918,11 @@
void
GicV2::clearInt(ContextID ctx, uint32_t int_num)
{
+ auto tc = sys->threads[ctx];
if (isFiq(ctx, int_num)) {
- platform->intrctrl->clear(ctx, ArmISA::INT_FIQ, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_FIQ,
0);
} else {
- platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_IRQ,
0);
}
}
@@ -936,7 +938,8 @@
void
GicV2::postDelayedInt(uint32_t cpu)
{
- platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
+ auto tc = sys->threads[cpu];
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_IRQ, 0);
--pendingDelayedInterrupts;
assert(pendingDelayedInterrupts >= 0);
if (pendingDelayedInterrupts == 0)
@@ -961,7 +964,8 @@
void
GicV2::postDelayedFiq(uint32_t cpu)
{
- platform->intrctrl->post(cpu, ArmISA::INT_FIQ, 0);
+ auto tc = sys->threads[cpu];
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_FIQ, 0);
--pendingDelayedInterrupts;
assert(pendingDelayedInterrupts >= 0);
if (pendingDelayedInterrupts == 0)
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index fbf03ad..f928a1e 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -51,7 +51,6 @@
#include "arch/arm/interrupts.hh"
#include "base/addr_range.hh"
#include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
#include "dev/arm/base_gic.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"
diff --git a/src/dev/arm/gic_v2m.hh b/src/dev/arm/gic_v2m.hh
index 9001adc..afdd89f 100644
--- a/src/dev/arm/gic_v2m.hh
+++ b/src/dev/arm/gic_v2m.hh
@@ -45,7 +45,6 @@
#define __DEV_ARM_GIC_V2M_H__
#include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
#include "dev/arm/base_gic.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 1f74209..bed264e 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -40,7 +40,7 @@
#include "dev/arm/gic_v3.hh"
-#include "cpu/intr_control.hh"
+#include "cpu/base.hh"
#include "debug/GIC.hh"
#include "debug/Interrupt.hh"
#include "dev/arm/gic_v3_cpu_interface.hh"
@@ -204,8 +204,9 @@
void
Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
{
- platform->intrctrl->post(cpu, int_type, 0);
- ArmSystem::callClearStandByWfi(sys->threads[cpu]);
+ auto tc = sys->threads[cpu];
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), int_type, 0);
+ ArmSystem::callClearStandByWfi(tc);
}
bool
@@ -218,19 +219,22 @@
void
Gicv3::deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
{
- platform->intrctrl->clear(cpu, int_type, 0);
+ auto tc = sys->threads[cpu];
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_type, 0);
}
void
Gicv3::deassertAll(uint32_t cpu)
{
- platform->intrctrl->clearAll(cpu);
+ auto tc = sys->threads[cpu];
+ tc->getCpuPtr()->clearInterrupts(tc->threadId());
}
bool
Gicv3::haveAsserted(uint32_t cpu) const
{
- return platform->intrctrl->havePosted(cpu);
+ auto tc = sys->threads[cpu];
+ return tc->getCpuPtr()->checkInterrupts(tc->threadId());
}
Gicv3Redistributor *
diff --git a/src/dev/arm/realview.cc b/src/dev/arm/realview.cc
index b46aacb..5cdac9e 100644
--- a/src/dev/arm/realview.cc
+++ b/src/dev/arm/realview.cc
@@ -48,13 +48,11 @@
#include <string>
#include <vector>
-#include "cpu/intr_control.hh"
#include "dev/arm/base_gic.hh"
-#include "sim/system.hh"
RealView::RealView(const Params &p)
- : Platform(p), system(p.system), gic(nullptr)
+ : Platform(p), gic(nullptr)
{}
void
diff --git a/src/dev/arm/realview.hh b/src/dev/arm/realview.hh
index 75def2f..065b753 100644
--- a/src/dev/arm/realview.hh
+++ b/src/dev/arm/realview.hh
@@ -52,25 +52,15 @@
class BaseGic;
class IdeController;
-class System;
class RealView : public Platform
{
public:
- /** Pointer to the system */
- System *system;
-
BaseGic *gic;
public:
using Params = RealViewParams;
- /**
- * Constructor for the Tsunami Class.
- * @param name name of the object
- * @param s system the object belongs to
- * @param intctrl pointer to the interrupt controller
- */
RealView(const Params &p);
/** Give platform a pointer to interrupt controller */
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index bcc2598..764bc8a 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -39,6 +39,7 @@
#include "arch/arm/interrupts.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/VGIC.hh"
#include "dev/arm/base_gic.hh"
@@ -371,13 +372,15 @@
VGic::unPostVInt(uint32_t cpu)
{
DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu);
- platform->intrctrl->clear(cpu, ArmISA::INT_VIRT_IRQ, 0);
+ auto tc = platform->system->threads[cpu];
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ,
0);
}
void
VGic::processPostVIntEvent(uint32_t cpu)
{
- platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);
+ auto tc = platform->system->threads[cpu];
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ,
0);
}
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index f94532d..63859f0 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -55,7 +55,6 @@
#include "base/addr_range.hh"
#include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"
#include "params/VGic.hh"
diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index 18fa219..e6e5b98 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -50,7 +50,6 @@
class Malta(Platform):
type = 'Malta'
cxx_header = "dev/mips/malta.hh"
- system = Param.System(Parent.any, "system")
cchip = MaltaCChip(pio_addr=0x801a0000000)
io = MaltaIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0xBFD003F8)
diff --git a/src/dev/mips/malta.cc b/src/dev/mips/malta.cc
index f9a0f22..69c56a5 100644
--- a/src/dev/mips/malta.cc
+++ b/src/dev/mips/malta.cc
@@ -36,7 +36,6 @@
#include <string>
#include <vector>
-#include "cpu/intr_control.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"
@@ -44,7 +43,7 @@
#include "sim/system.hh"
Malta::Malta(const Params &p)
- : Platform(p), system(p.system)
+ : Platform(p)
{
for (int i = 0; i < Malta::Max_CPUs; i++)
intr_sum_type[i] = 0;
diff --git a/src/dev/mips/malta.hh b/src/dev/mips/malta.hh
index e99bd30..3b7f99f 100644
--- a/src/dev/mips/malta.hh
+++ b/src/dev/mips/malta.hh
@@ -56,9 +56,6 @@
/** Max number of CPUs in a Malta */
static const int Max_CPUs = 64;
- /** Pointer to the system */
- System *system;
-
/** Pointer to the MaltaIO device which has the RTC */
MaltaIO *io;
@@ -72,12 +69,6 @@
int ipi_pending[Malta::Max_CPUs];
public:
- /**
- * Constructor for the Malta Class.
- * @param name name of the object
- * @param s system the object belongs to
- * @param intctrl pointer to the interrupt controller
- */
typedef MaltaParams Params;
Malta(const Params &p);
diff --git a/src/dev/mips/malta_cchip.cc b/src/dev/mips/malta_cchip.cc
index 711731b..e845ba0 100644
--- a/src/dev/mips/malta_cchip.cc
+++ b/src/dev/mips/malta_cchip.cc
@@ -37,7 +37,7 @@
#include <vector>
#include "base/trace.hh"
-#include "cpu/intr_control.hh"
+#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
@@ -106,7 +106,8 @@
for (int i=0; i < size; i++) {
//Note: Malta does not use index, but this was added to use the
//pre-existing implementation
- malta->intrctrl->post(i, interrupt, 0);
+ auto tc = sys->threads[i];
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), interrupt, 0);
DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
i, interrupt);
}
@@ -121,7 +122,8 @@
for (int i=0; i < size; i++) {
//Note: Malta does not use index, but this was added to use the
//pre-existing implementation
- malta->intrctrl->clear(i, interrupt, 0);
+ auto tc = sys->threads[i];
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), interrupt, 0);
DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
i, interrupt);
}
diff --git a/src/dev/platform.cc b/src/dev/platform.cc
index a0fa153..4d06a09 100644
--- a/src/dev/platform.cc
+++ b/src/dev/platform.cc
@@ -29,16 +29,8 @@
#include "dev/platform.hh"
#include "base/logging.hh"
-#include "sim/sim_exit.hh"
-Platform::Platform(const Params &p)
- : SimObject(p), intrctrl(p.intrctrl)
-{
-}
-
-Platform::~Platform()
-{
-}
+Platform::Platform(const Params &p) : SimObject(p), system(p.system) {}
void
Platform::postPciInt(int line)
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index 3b586c6..572842a 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -40,22 +40,18 @@
#include "params/Platform.hh"
#include "sim/sim_object.hh"
-class IntrControl;
class Terminal;
class Uart;
class System;
-
class Platform : public SimObject
{
public:
- /** Pointer to the interrupt controller */
- IntrControl *intrctrl;
+ System *system;
- public:
typedef PlatformParams Params;
Platform(const Params &p);
- virtual ~Platform();
+ virtual ~Platform() = default;
/**
* Cause the cpu to post a serial interrupt to the CPU.
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
index 0c01749..a9cf440 100644
--- a/src/dev/riscv/Clint.py
+++ b/src/dev/riscv/Clint.py
@@ -49,7 +49,6 @@
"""
type = 'Clint'
cxx_header = 'dev/riscv/clint.hh'
- intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
int_pin = IntSinkPin('Pin to receive RTC signal')
pio_size = Param.Addr(0xC000, "PIO Size")
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 722b404..07b6806 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -97,7 +97,6 @@
"""
type = 'HiFive'
cxx_header = "dev/riscv/hifive.hh"
- system = Param.System(Parent.any, "system")
# CLINT
clint = Param.Clint(Clint(pio_addr=0x2000000), "CLINT")
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index a8c97c8..42b3f44 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -48,7 +48,6 @@
"""
type = 'Plic'
cxx_header = 'dev/riscv/plic.hh'
- intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
pio_size = Param.Addr(0x4000000, "PIO Size")
n_src = Param.Int("Number of interrupt sources")
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index ced9122..21a4d93 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -37,6 +37,7 @@
#include "dev/riscv/clint.hh"
+#include "cpu/base.hh"
#include "debug/Clint.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@@ -48,7 +49,6 @@
Clint::Clint(const Params ¶ms) :
BasicPioDevice(params, params.pio_size),
system(params.system),
- intrctrl(params.intrctrl),
signal(params.name + ".signal", 0, this),
registers(params.name + ".registers", params.pio_addr, this)
{
@@ -63,22 +63,25 @@
for (int context_id = 0; context_id < nThread; context_id++) {
+ auto tc = system->threads[context_id];
+
// Update misc reg file
- ISA* isa = dynamic_cast<ISA*>(
- system->threads[context_id]->getIsaPtr());
+ ISA* isa = dynamic_cast<ISA*>(tc->getIsaPtr());
isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
// Post timer interrupt
uint64_t mtimecmp = registers.mtimecmp[context_id].get();
if (mtime >= mtimecmp) {
- if (mtime == mtimecmp) {
- DPRINTF(Clint,
- "MTIP posted - thread: %d, mtime: %d,
mtimecmp: %d\n",
- context_id, mtime, mtimecmp);
- }
- intrctrl->post(context_id, ExceptionCode::INT_TIMER_MACHINE,
0);
+ if (mtime == mtimecmp) {
+ DPRINTF(Clint,
+ "MTIP posted - thread: %d, mtime: %d, mtimecmp: %d\n",
+ context_id, mtime, mtimecmp);
+ }
+ tc->getCpuPtr()->postInterrupt(tc->threadId(),
+ ExceptionCode::INT_TIMER_MACHINE, 0);
} else {
- intrctrl->clear(context_id, ExceptionCode::INT_TIMER_MACHINE,
0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(),
+ ExceptionCode::INT_TIMER_MACHINE, 0);
}
}
}
@@ -137,15 +140,14 @@
{
reg.update(data);
assert(data <= 1);
+ auto tc = system->threads[thread_id];
if (data > 0) {
- DPRINTF(Clint,
- "MSIP posted - thread: %d\n", thread_id);
- intrctrl->post(thread_id,
+ DPRINTF(Clint, "MSIP posted - thread: %d\n", thread_id);
+ tc->getCpuPtr()->postInterrupt(tc->threadId(),
ExceptionCode::INT_SOFTWARE_MACHINE, 0);
} else {
- DPRINTF(Clint,
- "MSIP cleared - thread: %d\n", thread_id);
- intrctrl->clear(thread_id,
+ DPRINTF(Clint, "MSIP cleared - thread: %d\n", thread_id);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(),
ExceptionCode::INT_SOFTWARE_MACHINE, 0);
}
};
diff --git a/src/dev/riscv/clint.hh b/src/dev/riscv/clint.hh
index 05fdc4e..2602928 100644
--- a/src/dev/riscv/clint.hh
+++ b/src/dev/riscv/clint.hh
@@ -40,7 +40,6 @@
#include "arch/riscv/interrupts.hh"
#include "arch/riscv/registers.hh"
-#include "cpu/intr_control.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "dev/mc146818.hh"
@@ -71,7 +70,6 @@
// Params
protected:
System *system;
- IntrControl *intrctrl;
int nThread;
IntSinkPin<Clint> signal;
diff --git a/src/dev/riscv/hifive.cc b/src/dev/riscv/hifive.cc
index 543153a..bb376bb 100644
--- a/src/dev/riscv/hifive.cc
+++ b/src/dev/riscv/hifive.cc
@@ -45,7 +45,7 @@
using namespace RiscvISA;
HiFive::HiFive(const Params ¶ms) :
- Platform(params), system(params.system),
+ Platform(params),
clint(params.clint), plic(params.plic),
uartIntID(params.uart_int_id)
{
diff --git a/src/dev/riscv/hifive.hh b/src/dev/riscv/hifive.hh
index afa65c1..4e4e139 100644
--- a/src/dev/riscv/hifive.hh
+++ b/src/dev/riscv/hifive.hh
@@ -48,7 +48,6 @@
class HiFive : public Platform
{
public:
- System *system;
Clint *clint;
Plic *plic;
int uartIntID;
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 2183183..f6f9239 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -41,6 +41,7 @@
#include <algorithm>
#include "arch/riscv/registers.hh"
+#include "cpu/base.hh"
#include "debug/Plic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@@ -52,7 +53,6 @@
Plic::Plic(const Params ¶ms) :
BasicPioDevice(params, params.pio_size),
system(params.system),
- intrctrl(params.intrctrl),
nSrc(params.n_src),
registers(params.name, pioAddr, this),
update([this]{updateOutput();}, name() + ".update")
@@ -444,25 +444,22 @@
int int_id = (i & 1) ?
ExceptionCode::INT_EXT_SUPER : ExceptionCode::INT_EXT_MACHINE;
+ auto tc = system->threads[thread_id];
uint32_t max_id = output.maxID[i];
uint32_t priority = output.maxPriority[i];
uint32_t threshold = registers.threshold[i].get();
if (priority > threshold && max_id > 0 && lastID[i] == 0) {
- DPRINTF(Plic,
- "Int posted - thread: %d, int id: %d, ",
- thread_id, int_id);
- DPRINTFR(Plic,
- "pri: %d, thres: %d\n", priority, threshold);
- intrctrl->post(thread_id, int_id, 0);
+ DPRINTF(Plic, "Int posted - thread: %d, int id: %d, ",
+ thread_id, int_id);
+ DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), int_id, 0);
} else {
if (priority > 0) {
- DPRINTF(Plic,
- "Int filtered - thread: %d, int id: %d, ",
- thread_id, int_id);
- DPRINTFR(Plic,
- "pri: %d, thres: %d\n", priority, threshold);
+ DPRINTF(Plic, "Int filtered - thread: %d, int id: %d, ",
+ thread_id, int_id);
+ DPRINTFR(Plic, "pri: %d, thres: %d\n", priority,
threshold);
}
- intrctrl->clear(thread_id, int_id, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_id, 0);
}
}
}
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index a33b79f..2515f1b 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -42,7 +42,6 @@
#include <map>
#include "arch/riscv/interrupts.hh"
-#include "cpu/intr_control.hh"
#include "dev/io_device.hh"
#include "dev/reg_bank.hh"
#include "mem/packet.hh"
@@ -97,7 +96,6 @@
// Params
protected:
System *system;
- IntrControl *intrctrl;
// Number of interrupt sources
int nSrc;
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index c98fb86..299d6b2 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -55,7 +55,6 @@
class T1000(Platform):
type = 'T1000'
cxx_header = "dev/sparc/t1000.hh"
- system = Param.System(Parent.any, "system")
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
#warn_access="Accessing Clock Unit -- Unimplemented!")
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index 4a4cb8b..deec07f 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -42,7 +42,7 @@
#include "arch/sparc/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "cpu/intr_control.hh"
+#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Iob.hh"
#include "dev/platform.hh"
@@ -51,8 +51,7 @@
#include "sim/faults.hh"
#include "sim/system.hh"
-Iob::Iob(const Params &p)
- : PioDevice(p), ic(p.platform->intrctrl)
+Iob::Iob(const Params &p) : PioDevice(p)
{
iobManAddr = 0x9800000000ULL;
iobManSize = 0x0100000000ULL;
@@ -268,37 +267,44 @@
intCtl[devid].pend = true;
DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
devid, intMan[devid].cpu, intMan[devid].vector);
- ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC,
intMan[devid].vector);
+ auto tc = sys->threads[intMan[devid].cpu];
+ tc->getCpuPtr()->postInterrupt(tc->threadId(), SparcISA::IT_INT_VEC,
+ intMan[devid].vector);
}
void
Iob::generateIpi(Type type, int cpu_id, int vector)
{
- SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new
SparcISA::PowerOnReset();
+ SparcISA::SparcFault<SparcISA::PowerOnReset> *por =
+ new SparcISA::PowerOnReset();
if (cpu_id >= sys->threads.size())
return;
+ auto tc = sys->threads[cpu_id];
switch (type) {
case 0: // interrupt
- DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d
vec %d\n",
+ DPRINTF(Iob,
+ "Generating interrupt because of I/O write to cpu: "
+ "%d vec %d\n",
cpu_id, vector);
- ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
+ tc->getCpuPtr()->postInterrupt(
+ tc->threadId(), SparcISA::IT_INT_VEC, vector);
break;
case 1: // reset
warn("Sending reset to CPU: %d\n", cpu_id);
if (vector != por->trapType())
panic("Don't know how to set non-POR reset to cpu\n");
- por->invoke(sys->threads[cpu_id]);
- sys->threads[cpu_id]->activate();
+ por->invoke(tc);
+ tc->activate();
break;
case 2: // idle -- this means stop executing and don't wake on
interrupts
DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
- sys->threads[cpu_id]->halt();
+ tc->halt();
break;
case 3: // resume
DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n",
cpu_id);
- sys->threads[cpu_id]->activate();
+ tc->activate();
break;
default:
panic("Invalid type to generate ipi\n");
@@ -321,7 +327,9 @@
jBusData0[cpu_id] = d0;
jBusData1[cpu_id] = d1;
- ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
+ auto tc = sys->threads[cpu_id];
+ tc->getCpuPtr()->postInterrupt(
+ tc->threadId(), SparcISA::IT_INT_VEC, jIntVec);
return true;
}
diff --git a/src/dev/sparc/iob.hh b/src/dev/sparc/iob.hh
index 0f5fa95..4c981ed 100644
--- a/src/dev/sparc/iob.hh
+++ b/src/dev/sparc/iob.hh
@@ -37,8 +37,6 @@
#include "dev/io_device.hh"
#include "params/Iob.hh"
-class IntrControl;
-
const int MaxNiagaraProcs = 32;
// IOB Managment Addresses
const Addr IntManAddr = 0x0000;
@@ -71,7 +69,6 @@
class Iob : public PioDevice
{
private:
- IntrControl *ic;
Addr iobManAddr;
Addr iobManSize;
Addr iobJBusAddr;
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
index 0a90974..9b41844 100644
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/sparc/t1000.cc
@@ -36,12 +36,9 @@
#include <string>
#include <vector>
-#include "cpu/intr_control.hh"
-#include "sim/system.hh"
+#include "base/logging.hh"
-T1000::T1000(const Params &p)
- : Platform(p), system(p.system)
-{}
+T1000::T1000(const Params &p) : Platform(p) {}
void
T1000::postConsoleInt()
diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh
index 1cc8abf..9cf257e 100644
--- a/src/dev/sparc/t1000.hh
+++ b/src/dev/sparc/t1000.hh
@@ -39,15 +39,10 @@
#include "params/T1000.hh"
class IdeController;
-class System;
class T1000 : public Platform
{
public:
- /** Pointer to the system */
- System *system;
-
- public:
typedef T1000Params Params;
/**
* Constructor for the Tsunami Class.
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 87e3b0b..66d9e78 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -43,7 +43,6 @@
#include <string>
#include "base/cprintf.hh"
-#include "cpu/intr_control.hh"
#include "debug/IdeCtrl.hh"
#include "dev/storage/ide_disk.hh"
#include "mem/packet.hh"
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index ac7f034..c578403 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -38,18 +38,14 @@
#include "arch/x86/intmessage.hh"
#include "arch/x86/x86_traits.hh"
-#include "cpu/intr_control.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/i8254.hh"
#include "dev/x86/i8259.hh"
#include "dev/x86/south_bridge.hh"
#include "sim/system.hh"
-Pc::Pc(const Params &p)
- : Platform(p), system(p.system)
-{
- southBridge = NULL;
-}
+Pc::Pc(const Params &p) : Platform(p)
+{}
void
Pc::init()
diff --git a/src/dev/x86/pc.hh b/src/dev/x86/pc.hh
index 74e37dd..0e828e8 100644
--- a/src/dev/x86/pc.hh
+++ b/src/dev/x86/pc.hh
@@ -45,9 +45,7 @@
class Pc : public Platform
{
public:
- /** Pointer to the system */
- System *system;
- SouthBridge *southBridge;
+ SouthBridge *southBridge = nullptr;
public:
typedef PcParams Params;
diff --git a/tests/gem5/x86-boot-tests/system/system.py
b/tests/gem5/x86-boot-tests/system/system.py
index 7b9bd68..79bb666 100755
--- a/tests/gem5/x86-boot-tests/system/system.py
+++ b/tests/gem5/x86-boot-tests/system/system.py
@@ -232,8 +232,6 @@
self.iocache.cpu_side = self.iobus.master
self.iocache.mem_side = self.membus.slave
- self.intrctrl = IntrControl()
-
###############################################
# Add in a Bios information structure.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Gerrit-Change-Number: 43347
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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