Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41742 )
Change subject: arch-x86: Move (most) non-public values out of registers.hh.
......................................................................
arch-x86: Move (most) non-public values out of registers.hh.
The unnecessary DependenceTags is already being removed by another
pending change, and so is left in place for that to remove. Once that's
happened, the regs/*.hh includes can be removed, and there may be other
include related tangles to sort out.
Change-Id: I1c02aa8fd2f2045017609b70523b3519c2a92b03
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41742
Maintainer: Bobby R. Bruce <[email protected]>
Reviewed-by: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/x86/insts/static_inst.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/specialize.isa
M src/arch/x86/linux/linux.hh
M src/arch/x86/process.cc
M src/arch/x86/registers.hh
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/utility.cc
9 files changed, 24 insertions(+), 24 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/static_inst.cc
b/src/arch/x86/insts/static_inst.cc
index c23d014..6a9286e 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -240,13 +240,13 @@
os << "rip";
someAddr = true;
} else {
- if (scale != 0 && index != ZeroReg) {
+ if (scale != 0 && index != NUM_INTREGS) {
if (scale != 1)
ccprintf(os, "%d*", scale);
printReg(os, InstRegIndex(index), addressSize);
someAddr = true;
}
- if (base != ZeroReg) {
+ if (base != NUM_INTREGS) {
if (someAddr)
os << " + ";
printReg(os, InstRegIndex(base), addressSize);
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index d5dca43..556d73f 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -182,7 +182,7 @@
for (int i = 0; i < NumFloatRegs; ++i)
tc->setFloatRegFlat(i, src->readFloatRegFlat(i));
//copy condition-code regs
- for (int i = 0; i < NumCCRegs; ++i)
+ for (int i = 0; i < NUM_CCREGS; ++i)
tc->setCCRegFlat(i, src->readCCRegFlat(i));
copyMiscRegs(src, tc);
tc->pcState(src->pcState());
diff --git a/src/arch/x86/isa/specialize.isa
b/src/arch/x86/isa/specialize.isa
index 946732f..d6321f6 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -250,12 +250,12 @@
if opType.tag == "X":
env.addToDisassembly(
'''printMem(out, env.seg,
- 1, X86ISA::ZeroReg, X86ISA::INTREG_RSI, 0,
+ 1, X86ISA::NUM_INTREGS,
X86ISA::INTREG_RSI, 0,
env.addressSize, false);''')
else:
env.addToDisassembly(
'''printMem(out, SEGMENT_REG_ES,
- 1, X86ISA::ZeroReg, X86ISA::INTREG_RDI, 0,
+ 1, X86ISA::NUM_INTREGS,
X86ISA::INTREG_RDI, 0,
env.addressSize, false);''')
Name += "_M"
else:
diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index 6c98db8..28bab32 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -62,7 +62,7 @@
}
if (stack)
- ctc->setIntReg(X86ISA::StackPointerReg, stack);
+ ctc->setIntReg(X86ISA::INTREG_RSP, stack);
}
class SyscallABI {};
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index b46d4a3..164f17e 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -981,7 +981,7 @@
ThreadContext *tc = system->threads[contextIds[0]];
// Set the stack pointer register
- tc->setIntReg(StackPointerReg, stack_min);
+ tc->setIntReg(INTREG_RSP, stack_min);
// There doesn't need to be any segment base added in since we're
dealing
// with the flat segmentation model.
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 8f50d64..f52d4ea 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,23 +41,14 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
-#include "arch/x86/x86_traits.hh"
namespace X86ISA
{
-const int NumIntArchRegs = NUM_INTREGS;
-const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs +
NumImplicitIntRegs;
-const int NumCCRegs = NUM_CCREGS;
-
-// Each 128 bit xmm register is broken into two effective 64 bit registers.
-// Add 8 for the indices that are mapped over the fp stack
-const int NumFloatRegs =
- NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
-
// These enumerate all the registers for dependence tracking.
enum DependenceTags
{
@@ -66,14 +57,12 @@
// we just start at (1 << 7) == 128.
FP_Reg_Base = 128,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
+ Misc_Reg_Base = CC_Reg_Base + NUM_CCREGS,
Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
};
-// semantically meaningful register indices
-//There is no such register in X86
+// There is no such register in X86.
const int ZeroReg = NUM_INTREGS;
-const int StackPointerReg = INTREG_RSP;
// Not applicable to x86
using VecElem = ::DummyVecElem;
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 6cba603..963c111 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -148,6 +148,11 @@
{
return FLOATREG_FPR((top + index + 8) % 8);
}
+
+ // Each 128 bit xmm register is broken into two effective 64 bit
registers.
+ // Add 8 for the indices that are mapped over the fp stack
+ const int NumFloatRegs =
+ NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
}
#endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index aa26224..87b3190 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -169,6 +169,10 @@
index = (index - 4) | foldBit;
return (IntRegIndex)index;
}
+
+ const int NumIntArchRegs = NUM_INTREGS;
+ const int NumIntRegs =
+ NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
}
#endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 5293d6b..e3add56 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -40,11 +40,13 @@
#include "arch/x86/interrupts.hh"
#include "arch/x86/mmu.hh"
-#include "arch/x86/registers.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
#include "fputils/fp80.h"
-#include "sim/full_system.hh"
namespace X86ISA
{
9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1c02aa8fd2f2045017609b70523b3519c2a92b03
Gerrit-Change-Number: 41742
Gerrit-PatchSet: 11
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Brandon Potter <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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