Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41214 )
Change subject: arch-arm: Use src/base/fenv.hh instead of raw fenv.h.
......................................................................
arch-arm: Use src/base/fenv.hh instead of raw fenv.h.
This provides a layer of indirection where the rounding mode
setting/getting code will do nothing if fenv.h isn't available. At build
time, if fenv.h can't be found, a warning is printed.
Also, the include for fenv.h was guarded in the includes in the ISA
header, but the functions from it weren't guarded in the actual code.
Finally, the code was setting the rounding mode, but not setting it
back. That would mean running these instructions would set the rounding
mode in gem5 as a whole, affecting its other behaviors and any other
instructions that might expect the default rounding mode.
Change-Id: Ic5cc32773652f423e66d78f31b80c6604f2c4a49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41214
Tested-by: kokoro <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp.isa
2 files changed, 14 insertions(+), 11 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 16d4c1c..a09655b 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -108,17 +108,12 @@
#include "arch/generic/memhelpers.hh"
#include "base/condcodes.hh"
#include "base/crc.hh"
+#include "base/fenv.hh"
#include "cpu/base.hh"
-#include "sim/pseudo_inst.hh"
-
-#if defined(linux)
-#include <fenv.h>
-
-#endif
-
#include "debug/Arm.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
using namespace ArmISA;
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 07be0e1..a32b396 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -1106,11 +1106,13 @@
FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode);
- fesetround(FeRoundZero);
+ Gem5::RoundingMode old_rm = Gem5::getFpRound();
+ Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest_uw = vfpFpToFixed<float>(
FpOp1, false, 32, 0, true, {round_mode});
__asm__ __volatile__("" :: "m" (FpDest_uw));
+ Gem5::setFpRound(old_rm);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
@@ -1122,11 +1124,13 @@
double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode);
- fesetround(FeRoundZero);
+ Gem5::RoundingMode old_rm = Gem5::getFpRound();
+ Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
uint64_t result = vfpFpToFixed<double>(
cOp1, false, 32, 0, true, {round_mode});
__asm__ __volatile__("" :: "m" (result));
+ Gem5::setFpRound(old_rm);
finishVfp(fpscr, state, fpscr.fz);
FpDestP0_uw = result;
FpscrExc = fpscr;
@@ -1138,11 +1142,13 @@
FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode);
- fesetround(FeRoundZero);
+ Gem5::RoundingMode old_rm = Gem5::getFpRound();
+ Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest_sw = vfpFpToFixed<float>(
FpOp1, true, 32, 0, true, {round_mode});
__asm__ __volatile__("" :: "m" (FpDest_sw));
+ Gem5::setFpRound(old_rm);
finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr;
'''
@@ -1154,11 +1160,13 @@
double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode);
- fesetround(FeRoundZero);
+ Gem5::RoundingMode old_rm = Gem5::getFpRound();
+ Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
int64_t result = vfpFpToFixed<double>(
cOp1, true, 32, 0, true, {round_mode});
__asm__ __volatile__("" :: "m" (result));
+ Gem5::setFpRound(old_rm);
finishVfp(fpscr, state, fpscr.fz);
FpDestP0_uw = result;
FpscrExc = fpscr;
8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41214
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5cc32773652f423e66d78f31b80c6604f2c4a49
Gerrit-Change-Number: 41214
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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