Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44165 )
Change subject: dev-arm: Align gem5 to FVP Base PCI
......................................................................
dev-arm: Align gem5 to FVP Base PCI
The VExpress_GEM5_Foundation platform was reserving
a region of the memory map (@ 0x4 0000 0000) for PCI.
The Armv8-A FVP Foundation platform is not PCI capable at
the moment, so any PCI logic is really gem5 specific.
With this patch we are aligning gem5 to the FVP Base Platform,
which supports PCI and it is reserving 256GiB of memory
starting at 0x40 0000 0000 (256GiB).
Fast Models - Reference Manual - Version 11.8
At the moment we are still supporting a single DRAM range,
starting at 2GiB. So DRAM could overlap with the PCI memory
region though it is unlikely to happen in near future as
it would require a DRAM size > 254 GiB.
JIRA: https://gem5.atlassian.net/browse/GEM5-898
Change-Id: I506fd6696cdddc39d057602581cb16b30db3f7c7
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/dev/arm/RealView.py
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index a7080d8..229943c 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1374,12 +1374,19 @@
Reference for memory and interrupt map:
Armv8-A Foundation Platform - User Guide - Version 11.8
Document ID: 100961_1180_00_en
+
+ We are adding PCI capabilities to the Armv8-A FVP Foundation
+ Platform. We are enabling it by using the PCI memory map
+ of the Armv8-A FVP Base Platform:
+ Fast Models - Reference Manual - Version 11.8
+ Document ID: 100964_1108_00_en
"""
_off_chip_ranges = [
# CS1-CS5
AddrRange(0x0c000000, 0x20000000),
# External AXI interface (PCI)
AddrRange(0x40000000, 0x80000000),
+ AddrRange(0x4000000000, 0x800000000),
]
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
@@ -1393,7 +1400,7 @@
pci_host = GenericArmPciHost(
conf_base=0x40000000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x50000000,
- pci_mem_base=0x400000000,
+ pci_mem_base=0x4000000000,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
def _on_chip_devices(self):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I506fd6696cdddc39d057602581cb16b30db3f7c7
Gerrit-Change-Number: 44165
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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