Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44508 )
Change subject: arch: Add vec_reg.test & vec_pred_reg.test unittests
......................................................................
arch: Add vec_reg.test & vec_pred_reg.test unittests
Change-Id: Ieb85e0d35032585ead1e3b399f8eaf5dbc246d76
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/generic/SConscript
A src/arch/generic/vec_pred_reg.test.cc
A src/arch/generic/vec_reg.test.cc
3 files changed, 427 insertions(+), 0 deletions(-)
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index 3ad4878..18374cc 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -49,6 +49,9 @@
DebugFlag('TLB')
+GTest('vec_reg.test', 'vec_reg.test.cc')
+GTest('vec_pred_reg.test', 'vec_pred_reg.test.cc')
+
if env['TARGET_ISA'] == 'null':
Return()
diff --git a/src/arch/generic/vec_pred_reg.test.cc
b/src/arch/generic/vec_pred_reg.test.cc
new file mode 100644
index 0000000..b76d7df
--- /dev/null
+++ b/src/arch/generic/vec_pred_reg.test.cc
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <gtest/gtest.h>
+
+#include "arch/generic/vec_pred_reg.hh"
+
+TEST(VecPredReg, reset)
+{
+ constexpr size_t size = 4;
+ VecPredRegContainer<size, false> vec;
+
+ vec.reset();
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_FALSE(vec[idx]);
+ }
+}
+
+TEST(VecPredReg, set)
+{
+ constexpr size_t size = 4;
+ VecPredRegContainer<size, false> vec;
+
+ vec.set();
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_TRUE(vec[idx]);
+ }
+}
+
+template <bool T>
+class TwoDifferentVecPredRegsBase : public testing::Test
+{
+ protected:
+ static constexpr ssize_t size = 4;
+ VecPredRegContainer<size, T> pred1;
+ VecPredRegContainer<size, T> pred2;
+
+ void
+ SetUp() override
+ {
+ // Initializing with:
+ // 0,1,0,1
+ for (auto idx = 0; idx < size; idx++) {
+ pred1[idx] = (idx % 2);
+ }
+
+ // Initializing with:
+ // 1,0,1,0
+ for (auto idx = 0; idx < size; idx++) {
+ pred2[idx] = !(idx % 2);
+ }
+ }
+};
+
+using TwoDifferentVecPredRegs = TwoDifferentVecPredRegsBase<false>;
+using TwoPackedDifferentVecPredRegs = TwoDifferentVecPredRegsBase<true>;
+
+// Testing operator=
+TEST_F(TwoDifferentVecPredRegs, Assignment)
+{
+ pred2 = pred1;
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_EQ(pred2[idx], idx % 2);
+ }
+}
+
+// Testing operator==
+TEST_F(TwoDifferentVecPredRegs, Equality)
+{
+ // Equality check
+ ASSERT_TRUE(pred1 == pred1);
+ ASSERT_TRUE(pred2 == pred2);
+ ASSERT_FALSE(pred1 == pred2);
+}
+
+// Testing operator!=
+TEST_F(TwoDifferentVecPredRegs, Inequality)
+{
+ // Inequality check
+ ASSERT_TRUE(pred1 != pred2);
+ ASSERT_FALSE(pred1 != pred1);
+ ASSERT_FALSE(pred2 != pred2);
+}
+
+// Testing operator<<
+TEST_F(TwoDifferentVecPredRegs, Printing)
+{
+ {
+ std::ostringstream stream;
+ stream << pred1;
+ ASSERT_EQ(stream.str(), "0101");
+ }
+
+ {
+ std::ostringstream stream;
+ stream << pred2;
+ ASSERT_EQ(stream.str(), "1010");
+ }
+}
+
+// Testing to_number helper
+TEST_F(TwoDifferentVecPredRegs, ToNumber)
+{
+ to_number("1111", pred1);
+ to_number("1111", pred2);
+
+ // pred1 and pred2 are now the same
+ ASSERT_TRUE(pred1 == pred2);
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_TRUE(pred1[idx]);
+ ASSERT_TRUE(pred2[idx]);
+ }
+}
+
+// Testing VecPredReg view as uint8_t
+// pred1 is 0101
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// pred2 is 1010
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+TEST_F(TwoDifferentVecPredRegs, View8bit)
+{
+ auto pred1_view = pred1.as<uint8_t>();
+ auto pred2_view = pred2.as<uint8_t>();
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_EQ(pred1_view[idx], idx % 2);
+ ASSERT_EQ(pred2_view[idx], !(idx % 2));
+ }
+}
+
+// Testing VecPredReg view as uint16_t
+// pred1 is 0101
+// -> pred1_view[0] = false
+// -> pred1_view[1] = false
+// pred2 is 1010
+// -> pred2_view[0] = true
+// -> pred2_view[1] = true
+TEST_F(TwoDifferentVecPredRegs, View16bit)
+{
+ auto pred1_view = pred1.as<uint16_t>();
+ auto pred2_view = pred2.as<uint16_t>();
+
+ for (auto idx = 0; idx < size / sizeof(uint16_t); idx++) {
+ ASSERT_FALSE(pred1_view[idx]);
+ ASSERT_TRUE(pred2_view[idx]);
+ }
+}
+
+// Testing VecPredReg view as uint32_t
+// pred1 is 0101
+// -> pred1_view[0] = false
+// pred2 is 1010
+// -> pred2_view[0] = true
+TEST_F(TwoDifferentVecPredRegs, View32bit)
+{
+ auto pred1_view = pred1.as<uint32_t>();
+ auto pred2_view = pred2.as<uint32_t>();
+
+ ASSERT_FALSE(pred1_view[0]);
+ ASSERT_TRUE(pred2_view[0]);
+}
+
+// Testing VecPredReg view as uint8_t
+// pred1 is 0101
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// pred2 is 1010
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+TEST_F(TwoPackedDifferentVecPredRegs, View8bit)
+{
+ auto pred1_view = pred1.as<uint8_t>();
+ auto pred2_view = pred2.as<uint8_t>();
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_EQ(pred1_view[idx], idx % 2);
+ ASSERT_EQ(pred2_view[idx], !(idx % 2));
+ }
+}
+
+// Testing VecPredReg view as uint16_t
+// pred1 is 0101
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// pred2 is 1010
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+TEST_F(TwoPackedDifferentVecPredRegs, View16bit)
+{
+ auto pred1_view = pred1.as<uint16_t>();
+ auto pred2_view = pred2.as<uint16_t>();
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_EQ(pred1_view[idx], idx % 2);
+ ASSERT_EQ(pred2_view[idx], !(idx % 2));
+ }
+}
+
+// Testing VecPredReg view as uint32_t
+// pred1 is 0101
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// -> pred1_view[0] = false
+// -> pred1_view[1] = true
+// pred2 is 1010
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+// -> pred2_view[0] = true
+// -> pred2_view[1] = false
+TEST_F(TwoPackedDifferentVecPredRegs, View32bit)
+{
+ auto pred1_view = pred1.as<uint32_t>();
+ auto pred2_view = pred2.as<uint32_t>();
+
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_EQ(pred1_view[idx], idx % 2);
+ ASSERT_EQ(pred2_view[idx], !(idx % 2));
+ }
+}
diff --git a/src/arch/generic/vec_reg.test.cc
b/src/arch/generic/vec_reg.test.cc
new file mode 100644
index 0000000..6c3c1fd
--- /dev/null
+++ b/src/arch/generic/vec_reg.test.cc
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <gtest/gtest.h>
+
+#include "arch/generic/vec_reg.hh"
+
+TEST(VecReg, Size)
+{
+ {
+ // Minimum size
+ VecRegContainer<1> vec;
+ ASSERT_EQ(1, vec.size());
+ }
+
+ {
+ // Medium size
+ constexpr size_t size = MaxVecRegLenInBytes / 2;
+ VecRegContainer<size> vec;
+ ASSERT_EQ(size, vec.size());
+ }
+
+ {
+ // Maximum size
+ VecRegContainer<MaxVecRegLenInBytes> vec;
+ ASSERT_EQ(MaxVecRegLenInBytes, vec.size());
+ }
+}
+
+TEST(VecReg, Zero)
+{
+ constexpr size_t size = 16;
+ VecRegContainer<size> vec;
+ auto *vec_ptr = vec.as<uint8_t>();
+
+ // Initializing with non-zero value
+ for (auto idx = 0; idx < size; idx++) {
+ vec_ptr[idx] = 0xAA;
+ }
+
+ // zeroing the vector
+ vec.zero();
+
+ // checking if every vector element is set to zero
+ for (auto idx = 0; idx < size; idx++) {
+ ASSERT_EQ(vec_ptr[idx], 0);
+ }
+}
+
+class TwoDifferentVecRegs : public testing::Test
+{
+ protected:
+ VecRegContainer<16> vec1;
+ VecRegContainer<16> vec2;
+ uint8_t *vec1_ptr;
+ uint8_t *vec2_ptr;
+
+ void
+ SetUp() override
+ {
+ vec1_ptr = vec1.as<uint8_t>();
+ vec2_ptr = vec2.as<uint8_t>();
+
+ // Initializing with non-zero value vector1
+ for (auto idx = 0; idx < vec1.size(); idx++) {
+ vec1_ptr[idx] = 0xAA;
+ }
+
+ // Initializing with zero value vector2
+ for (auto idx = 0; idx < vec2.size(); idx++) {
+ vec2_ptr[idx] = 0;
+ }
+ }
+};
+
+// Testing operator=
+TEST_F(TwoDifferentVecRegs, Assignment)
+{
+ // Copying the vector
+ vec2 = vec1;
+
+ // Checking if vector2 elements are 0xAA
+ for (auto idx = 0; idx < vec2.size(); idx++) {
+ ASSERT_EQ(vec2_ptr[idx], 0xAA);
+ }
+}
+
+// Testing operator==
+TEST_F(TwoDifferentVecRegs, Equality)
+{
+ // Equality check
+ ASSERT_TRUE(vec1 == vec1);
+ ASSERT_TRUE(vec2 == vec2);
+ ASSERT_FALSE(vec1 == vec2);
+}
+
+// Testing operator!=
+TEST_F(TwoDifferentVecRegs, Inequality)
+{
+ // Inequality check
+ ASSERT_TRUE(vec1 != vec2);
+ ASSERT_FALSE(vec1 != vec1);
+ ASSERT_FALSE(vec2 != vec2);
+}
+
+// Testing operator<<
+TEST_F(TwoDifferentVecRegs, Printing)
+{
+ {
+ std::ostringstream stream;
+ stream << vec1;
+ ASSERT_EQ(stream.str(), "[aaaaaaaa_aaaaaaaa_aaaaaaaa_aaaaaaaa]");
+ }
+
+ {
+ std::ostringstream stream;
+ stream << vec2;
+ ASSERT_EQ(stream.str(), "[00000000_00000000_00000000_00000000]");
+ }
+}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44508
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieb85e0d35032585ead1e3b399f8eaf5dbc246d76
Gerrit-Change-Number: 44508
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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