Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40881 )
Change subject: arch-power: Use 64-bit registers and operands
......................................................................
arch-power: Use 64-bit registers and operands
This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with recent versions of the Power ISA. This
allows the registers to be used for both 32-bit and 64-bit
execution modes.
It should be noted that in 32-bit mode, the use of upper
word is dependent on the instruction being executed and in
some cases, this may be undefined.
Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40881
Tested-by: kokoro <[email protected]>
Reviewed-by: Gabe Black <[email protected]>
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Bobby R. Bruce <[email protected]>
---
M src/arch/power/isa/operands.isa
1 file changed, 10 insertions(+), 10 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index e77fde2..07415ba 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -41,10 +41,10 @@
def operands {{
# General Purpose Integer Reg Operands
- 'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
- 'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
- 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
- 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
+ 'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
+ 'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
+ 'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
+ 'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
# General Purpose Floating Point Reg Operands
'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
@@ -54,16 +54,16 @@
'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
# Memory Operand
- 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
+ 'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 8),
# Program counter and next
- 'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
- 'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
+ 'CIA': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 9),
+ 'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),
# Control registers
'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
- 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
- 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
+ 'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
+ 'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
# Setting as IntReg so things are stored as an integer, not double
@@ -72,5 +72,5 @@
# Registers for linked loads and stores
'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
- 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
+ 'RsvAddr': ('IntReg', 'ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
}};
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Gerrit-Change-Number: 40881
Gerrit-PatchSet: 5
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: lkcl <[email protected]>
Gerrit-MessageType: merged
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