Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/35245 )

Change subject: arch-arm: Move TLB stats update within the lookup method
......................................................................

arch-arm: Move TLB stats update within the lookup method

This is preparing for getTE becoming a MMU method: we still want
those stats to be part of the TLB class as they are TLB related

Change-Id: I7078385fd150144dc5dd4924961e4eaaa7e2446a
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35245
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
3 files changed, 32 insertions(+), 27 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index a81319e..8587443 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -386,7 +386,7 @@
// @TODO Should this always be the TLB or should we look in the stage2 TLB?
     TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
currState->vmid, currState->isHyp, currState->isSecure, true, false,
-            currState->el, false);
+            currState->el, false, BaseTLB::Read);

// Check if we still need to have a walk for this request. If the requesting // instruction has been squashed, or a previous walk has filled the TLB with
@@ -452,7 +452,7 @@
             currState = pendingQueue.front();
             te = tlb->lookup(currState->vaddr, currState->asid,
currState->vmid, currState->isHyp, currState->isSecure, true,
-                false, currState->el, false);
+                false, currState->el, false, BaseTLB::Read);
         } else {
             // Terminate the loop, nothing more to do
             currState = NULL;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index b1c4dff..bea1e16 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -126,7 +126,7 @@
     }

     TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false,
-                         aarch64 ? aarch64EL : EL1, false);
+                         aarch64 ? aarch64EL : EL1, false, BaseTLB::Read);
     if (!e)
         return false;
     pa = e->pAddr(va);
@@ -165,7 +165,7 @@
 TlbEntry*
 TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
             bool functional, bool ignore_asn, ExceptionLevel target_el,
-            bool in_host)
+            bool in_host, BaseTLB::Mode mode)
 {

     TlbEntry *retval = NULL;
@@ -203,6 +203,25 @@
             retval ? retval->global    : 0, retval ? retval->asid  : 0,
             retval ? retval->el        : 0);

+    // Updating stats if this was not a functional lookup
+    if (!functional) {
+        if (!retval) {
+            if (mode == BaseTLB::Execute)
+                stats.instMisses++;
+            else if (mode == BaseTLB::Write)
+                stats.writeMisses++;
+            else
+                stats.readMisses++;
+        } else {
+            if (mode == BaseTLB::Execute)
+                stats.instHits++;
+            else if (mode == BaseTLB::Write)
+               stats.writeHits++;
+            else
+                stats.readHits++;
+        }
+    }
+
     return retval;
 }

@@ -452,7 +471,7 @@
     bool hyp = target_el == EL2;

     te = lookup(mva, asn, vmid, hyp, secure_lookup, true, ignore_asn,
-                target_el, in_host);
+                target_el, in_host, BaseTLB::Read);
     while (te != NULL) {
         if (secure_lookup == !te->nstid) {
             DPRINTF(TLB, " -  %s\n", te->print());
@@ -460,7 +479,7 @@
             stats.flushedEntries++;
         }
         te = lookup(mva, asn, vmid, hyp, secure_lookup, true, ignore_asn,
-                    target_el, in_host);
+                    target_el, in_host, BaseTLB::Read);
     }
 }

@@ -1568,8 +1587,6 @@
     if (isStage2) {
         updateMiscReg(tc, tranType);
     }
-    bool is_fetch = (mode == Execute);
-    bool is_write = (mode == Write);

     Addr vaddr_tainted = req->getVaddr();
     Addr vaddr = 0;
@@ -1581,16 +1598,8 @@
         vaddr = vaddr_tainted;
     }
*te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el,
-                 false);
+                 false, mode);
     if (*te == NULL) {
- // Note, we are updating the stats for sw prefetching misses as well
-        if (is_fetch)
-            stats.instMisses++;
-        else if (is_write)
-            stats.writeMisses++;
-        else
-            stats.readMisses++;
-
         if (req->isPrefetch()) {
// if the request is a prefetch don't attempt to fill the TLB or go // any further with the memory access (here we can safely use the
@@ -1613,18 +1622,11 @@
             return fault;
         }

-        *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false,
-                     target_el, false);
+        *te = lookup(vaddr, asid, vmid, isHyp, is_secure, true, false,
+                     target_el, false, mode);
         if (!*te)
             printTlb();
         assert(*te);
-    } else {
-        if (is_fetch)
-            stats.instHits++;
-        else if (is_write)
-           stats.writeHits++;
-        else
-            stats.readHits++;
     }
     return NoFault;
 }
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 213311b..5aa72b5 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -217,12 +217,15 @@
      * @param hyp if the lookup is done from hyp mode
      * @param functional if the lookup should modify state
      * @param ignore_asn if on lookup asn should be ignored
+     * @param target_el selecting the translation regime
+     * @param in_host if we are in host (EL2&0 regime)
+     * @param mode to differentiate between read/writes/fetches.
      * @return pointer to TLB entry if it exists
      */
     TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
                      bool secure, bool functional,
                      bool ignore_asn, ExceptionLevel target_el,
-                     bool in_host);
+                     bool in_host, BaseTLB::Mode mode);

     virtual ~TLB();


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35245
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7078385fd150144dc5dd4924961e4eaaa7e2446a
Gerrit-Change-Number: 35245
Gerrit-PatchSet: 14
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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