Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44685 )
Change subject: sim: Trap into GDB instead of panicking on SEGV
......................................................................
sim: Trap into GDB instead of panicking on SEGV
When a segfault happens in the guest, report a SEGV trap to GDB (if
there is one attached) instead of bailing out immediately.
The obvious use-case for this, is the ability to debug guest crashes
in GDB in the standard manner.
The less-trivial use-case is for development of software in an
incomplete software stack (cf. Aarno-Engblom's "Virtual Platforms"
pp.105 et seq.) One particular example is Ingalls-Miranda simulation of
JIT compilers, where the VM's address space may be split between the
simulated and the real machine: in this case, GDB traps facilitate the
transparent illusion of an unbroken address space.
Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
---
M src/sim/faults.cc
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 501b5d1..13de0fc 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -40,6 +40,8 @@
#include "sim/faults.hh"
+#include <csignal>
+
#include "arch/decoder.hh"
#include "arch/locked_mem.hh"
#include "base/logging.hh"
@@ -94,15 +96,16 @@
Process *p = tc->getProcessPtr();
handled = p->fixupFault(vaddr);
}
- panic_if(!handled, "Page table fault when accessing virtual
address %#x",
- vaddr);
-
+ if (handled) return;
+ panic_if(tc->getSystemPtr()->trap_to_gdb(SIGSEGV),
+ "Page table fault when accessing virtual address %#x\n",
vaddr);
}
void
GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
- panic("Alignment fault when accessing virtual address %#x\n", vaddr);
+ panic_if(tc->getSystemPtr()->trap_to_gdb(SIGSEGV),
+ "Alignment fault when accessing virtual address %#x\n",
vaddr);
}
void GenericHtmFailureFault::invoke(ThreadContext *tc,
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 9fd312c..e8f881a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -495,6 +495,18 @@
lastWorkItemStarted.erase(p);
}
+bool
+System::trap_to_gdb(int signal) const
+{
+ if (!threads.size())
+ return true; /* true if we failed, so caller needs to panic */
+ auto *gdb = threads.thread(0).gdb;
+ if (!gdb)
+ return true;
+ gdb->trap(signal);
+ return false;
+}
+
void
System::printSystems()
{
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 6613217..fe02349 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -561,6 +561,8 @@
void workItemEnd(uint32_t tid, uint32_t workid);
+ bool trap_to_gdb(int signal) const;
+
protected:
/**
* Range for memory-mapped m5 pseudo ops. The range will be
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
Gerrit-Change-Number: 44685
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov <shinga...@gmail.com>
Gerrit-MessageType: newchange
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