See <https://jenkins.gem5.org/job/Weekly/19/display/redirect?page=changes>
Changes:
[shingarov] arch-power: Refactor CR field generation
[shingarov] arch-power: Use 64-bit registers and operands
[Giacomo Travaglini] mem: CFI Flash Memory implementation
[Giacomo Travaglini] dev-arm: Turn flash1 into a CFI Flash Memory
[Giacomo Travaglini] tests: Arm FS regressions using new guest binaries
[Giacomo Travaglini] tests: Use MatchFileRegex vierifier for realview
regressions
[Giacomo Travaglini] arch-arm: Move TLB stats update within the lookup method
[gabe.black] cpu: Merge the BaseDynInst and the BaseO3DynInst classes.
[gabe.black] cpu: Get rid of the unused eaSrcsReady method.
[gabe.black] cpu: De-templatize the BaseO3DynInst.
[gabe.black] arch-power: Fix power build.
[gabe.black] arch,cpu,sim: Move the null and nop StaticInstPtrs to their own
files.
[gabe.black] scons: Stop piggy-backing on the default tool for default settings.
[gabe.black] scons: Move the "duplicate" setting into gem5_env_defaults.py.
[gabe.black] scons: Move MakeAction into gem5_scons.
[yuhsingw] systemc: Extend TlmBridges to 512 bits
[Giacomo Travaglini] configs: Remove Ruby on ARM warning
[Giacomo Travaglini] util: Fix cpt_upgrader format string
[Giacomo Travaglini] util: Remove unused package import
[odanrc] scons: Allow declaring dependencies of tags
[gabe.black] sim: Minor cleanup of the System class.
[gabe.black] base: Improve handling of thread IDs for remote GDB.
[gabe.black] arch-sparc: Wrap overly long lines in the decoder definition.
[gabe.black] arch-sparc: Fix some bit manipulation bugs.
[gabe.black] arch,mem: Use szext instead of sext as appropriate.
[gabe.black] sim: Don't needlessly recreate ISA types in InstRecord.
[gabe.black] arch,cpu: Separate printing and serialization of VecPredReg.
[gabe.black] arch: Collapse unused size parameter from "as" VecPredReg method.
[gabe.black] cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.
[gabe.black] base: Streamline the "send" method of the BaseRemoteGDB class.
[gabe.black] base: Add a link to documentation in the remote GDB header file.
[gabe.black] cpu,sim: Set ThreadContext's ContextID right away.
[gabe.black] sim: Track ThreadContext-s in the Workload object.
[Giacomo Travaglini] util: Replace optparse with argparse
[hoanguyen] configs: Fix stats name in arm/fs_power.py
[Giacomo Travaglini] configs: restore_simpoint_checkpoint should be a boolean
[Giacomo Travaglini] configs, tests: Replace optparse with argparse
[shingarov] sim: Trap into GDB instead of panicking on SEGV
[gabe.black] cpu: Eliminate the isZeroReg() helper in RegId.
[gabe.black] cpu: Simplify the RegId class a little.
[alexandru.dutu] sim: Add pool specific allocators to SE mode
[gabe.black] arch-arm: Simplify the "mult" SIMD instructions with a BitUnion.
[gabe.black] base: Check the context ID when replacing a ThreadContext in GDB.
------------------------------------------
[...truncated 953.95 KB...]
[ SHCC] softfloat/f16_lt_quiet.c -> .os
[ SHCC] softfloat/f16_mulAdd.c -> .os
[ SHCC] softfloat/f16_mul.c -> .os
[ SHCC] softfloat/f16_rem.c -> .os
[ SHCC] softfloat/f16_roundToInt.c -> .os
[ SHCC] softfloat/f16_sqrt.c -> .os
[ SHCC] softfloat/f16_sub.c -> .os
[ SHCC] softfloat/f16_to_f128.c -> .os
[ SHCC] softfloat/f16_to_f32.c -> .os
[ SHCC] softfloat/f16_to_f64.c -> .os
[ SHCC] softfloat/f16_to_i32.c -> .os
[ SHCC] softfloat/f16_to_i32_r_minMag.c -> .os
[ SHCC] softfloat/f16_to_i64.c -> .os
[ SHCC] softfloat/f16_to_i64_r_minMag.c -> .os
[ SHCC] softfloat/f16_to_ui32.c -> .os
[ SHCC] softfloat/f16_to_ui32_r_minMag.c -> .os
[ SHCC] softfloat/f16_to_ui64.c -> .os
[ SHCC] softfloat/f16_to_ui64_r_minMag.c -> .os
[ SHCC] softfloat/f32_add.c -> .os
[ SHCC] softfloat/f32_classify.c -> .os
[ SHCC] softfloat/f32_div.c -> .os
[ SHCC] softfloat/f32_eq.c -> .os
[ SHCC] softfloat/f32_eq_signaling.c -> .os
[ SHCC] softfloat/f32_isSignalingNaN.c -> .os
[ SHCC] softfloat/f32_le.c -> .os
[ SHCC] softfloat/f32_le_quiet.c -> .os
[ SHCC] softfloat/f32_lt.c -> .os
[ SHCC] softfloat/f32_lt_quiet.c -> .os
[ SHCC] softfloat/f32_mulAdd.c -> .os
[ SHCC] softfloat/f32_mul.c -> .os
[ SHCC] softfloat/f32_rem.c -> .os
[ SHCC] softfloat/f32_roundToInt.c -> .os
[ SHCC] softfloat/f32_sqrt.c -> .os
[ SHCC] softfloat/f32_sub.c -> .os
[ SHCC] softfloat/f32_to_f128.c -> .os
[ SHCC] softfloat/f32_to_f16.c -> .os
[ SHCC] softfloat/f32_to_f64.c -> .os
[ SHCC] softfloat/f32_to_i32.c -> .os
[ SHCC] softfloat/f32_to_i32_r_minMag.c -> .os
[ SHCC] softfloat/f32_to_i64.c -> .os
[ SHCC] softfloat/f32_to_i64_r_minMag.c -> .os
[ SHCC] softfloat/f32_to_ui32.c -> .os
[ SHCC] softfloat/f32_to_ui32_r_minMag.c -> .os
[ SHCC] softfloat/f32_to_ui64.c -> .os
[ SHCC] softfloat/f32_to_ui64_r_minMag.c -> .os
[ SHCC] softfloat/f64_add.c -> .os
[ SHCC] softfloat/f64_classify.c -> .os
[ SHCC] softfloat/f64_div.c -> .os
[ SHCC] softfloat/f64_eq.c -> .os
[ SHCC] softfloat/f64_eq_signaling.c -> .os
[ SHCC] softfloat/f64_isSignalingNaN.c -> .os
[ SHCC] softfloat/f64_le.c -> .os
[ SHCC] softfloat/f64_le_quiet.c -> .os
[ SHCC] softfloat/f64_lt.c -> .os
[ SHCC] softfloat/f64_lt_quiet.c -> .os
[ SHCC] softfloat/f64_mulAdd.c -> .os
[ SHCC] softfloat/f64_mul.c -> .os
[ SHCC] softfloat/f64_rem.c -> .os
[ SHCC] softfloat/f64_roundToInt.c -> .os
[ SHCC] softfloat/f64_sqrt.c -> .os
[ SHCC] softfloat/f64_sub.c -> .os
[ SHCC] softfloat/f64_to_f128.c -> .os
[ SHCC] softfloat/f64_to_f16.c -> .os
[ SHCC] softfloat/f64_to_f32.c -> .os
[ SHCC] softfloat/f64_to_i32.c -> .os
[ SHCC] softfloat/f64_to_i32_r_minMag.c -> .os
[ SHCC] softfloat/f64_to_i64.c -> .os
[ SHCC] softfloat/f64_to_i64_r_minMag.c -> .os
[ SHCC] softfloat/f64_to_ui32.c -> .os
[ SHCC] softfloat/f64_to_ui32_r_minMag.c -> .os
[ SHCC] softfloat/f64_to_ui64.c -> .os
[ SHCC] softfloat/f64_to_ui64_r_minMag.c -> .os
[ SHCC] softfloat/i32_to_f128.c -> .os
[ SHCC] softfloat/i32_to_f16.c -> .os
[ SHCC] softfloat/i32_to_f32.c -> .os
[ SHCC] softfloat/i32_to_f64.c -> .os
[ SHCC] softfloat/i64_to_f128.c -> .os
[ SHCC] softfloat/i64_to_f16.c -> .os
[ SHCC] softfloat/i64_to_f32.c -> .os
[ SHCC] softfloat/i64_to_f64.c -> .os
[ SHCC] softfloat/s_add128.c -> .os
[ SHCC] softfloat/s_add256M.c -> .os
[ SHCC] softfloat/s_addCarryM.c -> .os
[ SHCC] softfloat/s_addComplCarryM.c -> .os
[ SHCC] softfloat/s_addMagsF128.c -> .os
[ SHCC] softfloat/s_addMagsF16.c -> .os
[ SHCC] softfloat/s_addMagsF32.c -> .os
[ SHCC] softfloat/s_addMagsF64.c -> .os
[ SHCC] softfloat/s_addM.c -> .os
[ SHCC] softfloat/s_approxRecip_1Ks.c -> .os
[ SHCC] softfloat/s_approxRecip32_1.c -> .os
[ SHCC] softfloat/s_approxRecipSqrt_1Ks.c -> .os
[ SHCC] softfloat/s_approxRecipSqrt32_1.c -> .os
[ SHCC] softfloat/s_commonNaNToF128UI.c -> .os
[ SHCC] softfloat/s_commonNaNToF16UI.c -> .os
[ SHCC] softfloat/s_commonNaNToF32UI.c -> .os
[ SHCC] softfloat/s_commonNaNToF64UI.c -> .os
[ SHCC] softfloat/s_compare128M.c -> .os
[ SHCC] softfloat/s_compare96M.c -> .os
[ SHCC] softfloat/s_countLeadingZeros16.c -> .os
[ SHCC] softfloat/s_countLeadingZeros32.c -> .os
[ SHCC] softfloat/s_countLeadingZeros64.c -> .os
[ SHCC] softfloat/s_countLeadingZeros8.c -> .os
[ SHCC] softfloat/s_eq128.c -> .os
[ SHCC] softfloat/s_f128UIToCommonNaN.c -> .os
[ SHCC] softfloat/s_f16UIToCommonNaN.c -> .os
[ SHCC] softfloat/s_f32UIToCommonNaN.c -> .os
[ SHCC] softfloat/s_f64UIToCommonNaN.c -> .os
[ SHCC] softfloat/s_le128.c -> .os
[ SHCC] softfloat/s_lt128.c -> .os
[ SHCC] softfloat/s_mul128By32.c -> .os
[ SHCC] softfloat/s_mul128MTo256M.c -> .os
[ SHCC] softfloat/s_mul128To256M.c -> .os
[ SHCC] softfloat/s_mul64ByShifted32To128.c -> .os
[ SHCC] softfloat/s_mul64To128.c -> .os
[ SHCC] softfloat/s_mul64To128M.c -> .os
[ SHCC] softfloat/s_mulAddF128.c -> .os
[ SHCC] softfloat/s_mulAddF16.c -> .os
[ SHCC] softfloat/s_mulAddF32.c -> .os
[ SHCC] softfloat/s_mulAddF64.c -> .os
[ SHCC] softfloat/s_negXM.c -> .os
[ SHCC] softfloat/s_normRoundPackToF128.c -> .os
[ SHCC] softfloat/s_normRoundPackToF16.c -> .os
[ SHCC] softfloat/s_normRoundPackToF32.c -> .os
[ SHCC] softfloat/s_normRoundPackToF64.c -> .os
[ SHCC] softfloat/s_normSubnormalF128Sig.c -> .os
[ SHCC] softfloat/s_normSubnormalF16Sig.c -> .os
[ SHCC] softfloat/s_normSubnormalF32Sig.c -> .os
[ SHCC] softfloat/s_normSubnormalF64Sig.c -> .os
[ SHCC] softfloat/softfloat_raiseFlags.c -> .os
[ SHCC] softfloat/softfloat_state.c -> .os
[ SHCC] softfloat/s_propagateNaNF128UI.c -> .os
[ SHCC] softfloat/s_propagateNaNF16UI.c -> .os
[ SHCC] softfloat/s_propagateNaNF32UI.c -> .os
[ SHCC] softfloat/s_propagateNaNF64UI.c -> .os
[ SHCC] softfloat/s_remStepMBy32.c -> .os
[ SHCC] softfloat/s_roundMToI64.c -> .os
[ SHCC] softfloat/s_roundMToUI64.c -> .os
[ SHCC] softfloat/s_roundPackMToI64.c -> .os
[ SHCC] softfloat/s_roundPackMToUI64.c -> .os
[ SHCC] softfloat/s_roundPackToF128.c -> .os
[ SHCC] softfloat/s_roundPackToF16.c -> .os
[ SHCC] softfloat/s_roundPackToF32.c -> .os
[ SHCC] softfloat/s_roundPackToF64.c -> .os
[ SHCC] softfloat/s_roundPackToI32.c -> .os
[ SHCC] softfloat/s_roundPackToI64.c -> .os
[ SHCC] softfloat/s_roundPackToUI32.c -> .os
[ SHCC] softfloat/s_roundPackToUI64.c -> .os
[ SHCC] softfloat/s_roundToI32.c -> .os
[ SHCC] softfloat/s_roundToI64.c -> .os
[ SHCC] softfloat/s_roundToUI32.c -> .os
[ SHCC] softfloat/s_roundToUI64.c -> .os
[ SHCC] softfloat/s_shiftRightJam128.c -> .os
[ SHCC] softfloat/s_shiftRightJam128Extra.c -> .os
[ SHCC] softfloat/s_shiftRightJam256M.c -> .os
[ SHCC] softfloat/s_shiftRightJam32.c -> .os
[ SHCC] softfloat/s_shiftRightJam64.c -> .os
[ SHCC] softfloat/s_shiftRightJam64Extra.c -> .os
[ SHCC] softfloat/s_shortShiftLeft128.c -> .os
[ SHCC] softfloat/s_shortShiftLeft64To96M.c -> .os
[ SHCC] softfloat/s_shortShiftRight128.c -> .os
[ SHCC] softfloat/s_shortShiftRightExtendM.c -> .os
[ SHCC] softfloat/s_shortShiftRightJam128.c -> .os
[ SHCC] softfloat/s_shortShiftRightJam128Extra.c -> .os
[ SHCC] softfloat/s_shortShiftRightJam64.c -> .os
[ SHCC] softfloat/s_shortShiftRightJam64Extra.c -> .os
[ SHCC] softfloat/s_shortShiftRightM.c -> .os
[ SHCC] softfloat/s_sub128.c -> .os
[ SHCC] softfloat/s_sub1XM.c -> .os
[ SHCC] softfloat/s_sub256M.c -> .os
[ SHCC] softfloat/s_subMagsF128.c -> .os
[ SHCC] softfloat/s_subMagsF16.c -> .os
[ SHCC] softfloat/s_subMagsF32.c -> .os
[ SHCC] softfloat/s_subMagsF64.c -> .os
[ SHCC] softfloat/s_subM.c -> .os
[ SHCC] softfloat/ui32_to_f128.c -> .os
[ SHCC] softfloat/ui32_to_f16.c -> .os
[ SHCC] softfloat/ui32_to_f32.c -> .os
[ SHCC] softfloat/ui32_to_f64.c -> .os
[ SHCC] softfloat/ui64_to_f128.c -> .os
[ SHCC] softfloat/ui64_to_f16.c -> .os
[ SHCC] softfloat/ui64_to_f32.c -> .os
[ SHCC] softfloat/ui64_to_f64.c -> .os
[ AR] -> softfloat/libsoftfloat.a
[ RANLIB] -> softfloat/libsoftfloat.a
[ LINK] -> GCN3_X86/gem5.opt
/usr/include/net/if.h:136:7: warning: type 'union <anon>' violates one
definition rule [-Wodr]
{
^
/usr/include/linux/if.h:233:8: note: a different type is defined in another
translation unit
union {
^
/usr/include/net/if.h:148:12: note: the first difference of corresponding
definitions is field 'ifru_data'
__caddr_t ifru_data;
^
/usr/include/linux/if.h:245:10: note: a field of same name but different type
is defined in another translation unit
void * ifru_data;
^
<built-in>: note: type 'char' should match type 'void'
/usr/include/net/if.h:126:8: warning: type 'struct ifreq' violates one
definition rule [-Wodr]
struct ifreq
^
/usr/include/linux/if.h:226:8: note: a different type is defined in another
translation unit
struct ifreq {
^
/usr/include/net/if.h:149:9: note: the first difference of corresponding
definitions is field 'ifr_ifru'
} ifr_ifru;
^
/usr/include/linux/if.h:247:4: note: a field of same name but different type is
defined in another translation unit
} ifr_ifru;
^
/usr/include/net/if.h:136:7: note: type 'union <anon>' should match type 'union
<anon>' that itself violate one definition rule
{
^
/usr/include/linux/if.h:233:8: note: the incompatible type is defined here
union {
^
scons: done building targets.
*** Summary of Warnings ***
Warning: Can't enable object file debug section compression
Warning: Can't enable executable debug section compression
Warning: Couldn't find any HDF5 C++ libraries. Disabling HDF5 support.
+ wget -qN http://dist.gem5.org/dist/develop/test-progs/square/square.o
+ mkdir -p tests/testing-results
+ pwd
+ pwd
+ pwd
+ docker run -u : --volume
<https://jenkins.gem5.org/job/Weekly/ws/>:<https://jenkins.gem5.org/job/Weekly/ws/>
-w <https://jenkins.gem5.org/job/Weekly/ws/> gcr.io/gem5-test/gcn-gpu:latest
build/GCN3_X86/gem5.opt configs/example/apu_se.py -n2 -c square.o
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "build/GCN3_X86/python/m5/main.py", line 455, in main
exec(filecode, scope)
File "configs/example/apu_se.py", line 189, in <module>
parser.add_option("--dgpu", action="store_true", default=False,
AttributeError: 'ArgumentParser' object has no attribute 'add_option'
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version [DEVELOP-FOR-V21.1]
gem5 compiled Apr 23 2021 09:47:36
gem5 started Apr 23 2021 09:57:05
gem5 executing on ea85a0a42ecc, pid 1
command line: build/GCN3_X86/gem5.opt configs/example/apu_se.py -n2 -c square.o
info: Standard input is not a terminal, disabling listeners.
Build step 'Execute shell' marked build as failure
Archiving artifacts
Recording test results
[Checks API] No suitable checks publisher found.
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