Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/44845 )

Change subject: sim: Use memPools in SE mode only
......................................................................

sim: Use memPools in SE mode only

memPools have been added by:

https://gem5-review.googlesource.com/c/public/gem5/+/42215

and are supposed to be used in SE mode only.
Current code is assuming there is at least one memory which is visible
to the OS/bootloader (conf_table_reported = True). This makes sense
in SE mode as it emulates the OS, but it shouldn't be enforced
in FS baremetal simulations

With this patch we are making sure memPools are used in SE mode
only.

Change-Id: Icebb7dafc18a6fdad0f9b16e5a988270bbebb9eb
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/sim/system.cc
1 file changed, 16 insertions(+), 11 deletions(-)



diff --git a/src/sim/system.cc b/src/sim/system.cc
index b4866ba..1bbda6b 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -233,18 +233,20 @@
     }
 #endif

-    AddrRangeList memories = physmem.getConfAddrRanges();
-    assert(!memories.empty());
-    for (const auto &memory : memories) {
-        assert(!memory.interleaved());
-        memPools.emplace_back(this, memory.start(), memory.end());
-    }
+    if (!FullSystem) {
+        AddrRangeList memories = physmem.getConfAddrRanges();
+        assert(!memories.empty());
+        for (const auto &memory : memories) {
+            assert(!memory.interleaved());
+            memPools.emplace_back(this, memory.start(), memory.end());
+        }

-    /*
-     * Set freePage to what it was before Gabe Black's page table changes
-     * so allocations don't trample the page table entries.
-     */
-    memPools[0].setFreePage(memPools[0].freePage() + 70);
+        /*
+ * Set freePage to what it was before Gabe Black's page table changes
+         * so allocations don't trample the page table entries.
+         */
+        memPools[0].setFreePage(memPools[0].freePage() + 70);
+    }

     // check if the cache line size is a value known to work
     if (_cacheLineSize != 16 && _cacheLineSize != 32 &&
@@ -377,18 +379,21 @@
 Addr
 System::allocPhysPages(int npages, int poolID)
 {
+    assert(!FullSystem);
     return memPools[poolID].allocate(npages);
 }

 Addr
 System::memSize(int poolID) const
 {
+    assert(!FullSystem);
     return memPools[poolID].totalBytes();
 }

 Addr
 System::freeMemSize(int poolID) const
 {
+    assert(!FullSystem);
     return memPools[poolID].freeBytes();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icebb7dafc18a6fdad0f9b16e5a988270bbebb9eb
Gerrit-Change-Number: 44845
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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