Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42966 )
Change subject: arch,base,cpu: Move some type aliases into base/types.hh.
......................................................................
arch,base,cpu: Move some type aliases into base/types.hh.
The arch/generic/types.hh header includes some more complicated types
which in turn bring in more dependencies, adding baggage when other code
only needs the simple RegIndex or ElemIndex types. Also the RegVal type
alias is already in base/types.hh. It doesn't really make sense to have
RegVal in one header and RegIndex in another.
Change-Id: I1360652598b5fa59e0632b1ee0e0535ace2ba563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42966
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Bobby R. Bruce <[email protected]>
---
M src/arch/generic/types.hh
M src/base/types.hh
M src/cpu/reg_class.hh
3 files changed, 15 insertions(+), 14 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 76df835..0f1e837 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -42,21 +42,11 @@
#define __ARCH_GENERIC_TYPES_HH__
#include <iostream>
-#include <limits>
#include "base/trace.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
-// Logical register index type.
-typedef uint16_t RegIndex;
-
-/** Logical vector register elem index type. */
-using ElemIndex = uint16_t;
-
-/** ElemIndex value that indicates that the register is not a vector. */
-#define ILLEGAL_ELEM_INDEX std::numeric_limits<ElemIndex>::max()
-
namespace GenericISA
{
diff --git a/src/base/types.hh b/src/base/types.hh
index 5e9a207..5f4c741 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -38,6 +38,7 @@
#include <inttypes.h>
#include <cassert>
+#include <limits>
#include <memory>
#include <ostream>
#include <stdexcept>
@@ -166,7 +167,17 @@
const Addr MaxAddr = (Addr)-1;
-typedef uint64_t RegVal;
+using RegVal = uint64_t;
+
+// Logical register index type.
+using RegIndex = uint16_t;
+
+/** Logical vector register elem index type. */
+using ElemIndex = uint16_t;
+
+/** ElemIndex value that indicates that the register is not a vector. */
+static const ElemIndex IllegalElemIndex =
+ std::numeric_limits<ElemIndex>::max();
static inline uint32_t
floatToBits32(float val)
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 37207a2..d11dc2e 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -44,8 +44,8 @@
#include <cassert>
#include <cstddef>
-#include "arch/generic/types.hh"
#include "arch/registers.hh"
+#include "base/types.hh"
#include "config/the_isa.hh"
/** Enumerate the classes of registers. */
@@ -100,13 +100,13 @@
RegId() : RegId(IntRegClass, 0) {}
RegId(RegClass reg_class, RegIndex reg_idx)
- : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
+ : RegId(reg_class, reg_idx, IllegalElemIndex) {}
explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex
elem_idx)
: regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
numPinnedWrites(0)
{
- if (elemIdx == ILLEGAL_ELEM_INDEX) {
+ if (elemIdx == IllegalElemIndex) {
panic_if(regClass == VecElemClass,
"Creating vector physical index w/o element index");
} else {
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1360652598b5fa59e0632b1ee0e0535ace2ba563
Gerrit-Change-Number: 42966
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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