Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40887 )
Change subject: arch-power: Fix branch conditional instructions
......................................................................
arch-power: Fix branch conditional instructions
Among the register-based conditional branch instructions,
the ones using CTR should not decrement CTR when the bit
corresponding to this action is set in the BO field of
the instruction. In this case, the instruction should be
considered invalid. This fixes the following instructions.
* Branch Conditional to Count Register (bcctr[l])
Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40887
Reviewed-by: Boris Shingarov <shinga...@gmail.com>
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 17 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 3ea6d8c..771a822 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -69,6 +69,7 @@
def bitfield FXM <19:12>;
// Branch fields
+def bitfield BO <25:21>;
def bitfield LK <0>;
def bitfield AA <1>;
diff --git a/src/arch/power/isa/formats/branch.isa
b/src/arch/power/isa/formats/branch.isa
index 2f50627..b970bc0 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -156,8 +156,10 @@
# Setup the 2 code versions and add code to update LR if necessary
if checkCTR:
code = GetCtrCondCode(code)
+ decode_template = CheckLkDecode
else:
code = GetCondCode(code)
+ decode_template = CheckBoLkDecode
code_lk1 = code + updateLrCode
inst_flags_lk1 = inst_flags + [ 'IsCall' ]
@@ -168,10 +170,10 @@
# Generate the classes
(header_output, decoder_output, decode_block, exec_output) = \
GenAluOp(name, Name, 'BranchRegCondOp', code, inst_flags,
- CheckLkDecode, BasicConstructor)
+ decode_template, BasicConstructor)
(header_output_lk1, decoder_output_lk1, _, exec_output_lk1) = \
GenAluOp(name, Name + 'LkSet', 'BranchRegCondOp', code_lk1,
- inst_flags_lk1, CheckLkDecode, BasicConstructor)
+ inst_flags_lk1, decode_template, BasicConstructor)
# Finally, add to the other outputs
header_output += header_output_lk1
diff --git a/src/arch/power/isa/formats/util.isa
b/src/arch/power/isa/formats/util.isa
index 34bebb0..529d07b 100644
--- a/src/arch/power/isa/formats/util.isa
+++ b/src/arch/power/isa/formats/util.isa
@@ -111,6 +111,18 @@
}
}};
+def template CheckBoLkDecode {{
+ {
+ if (!bits(BO, 2)) {
+ return new Unknown(machInst);
+ } else if (LK == 0) {
+ return new %(class_name)s(machInst);
+ } else {
+ return new %(class_name)sLkSet(machInst);
+ }
+ }
+}};
+
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Gerrit-Change-Number: 40887
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-Reviewer: Boris Shingarov <shinga...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: lkcl <luke.leigh...@gmail.com>
Gerrit-MessageType: merged
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