Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45409 )
Change subject: gpu-compute: Rename prefetch variable as isPrefetch
......................................................................
gpu-compute: Rename prefetch variable as isPrefetch
Pave the way for a prefetch namespace.
Change-Id: I4372abb5603eb6a920f7ff127cde54cb24e31377
Signed-off-by: Daniel R. Carvalho <[email protected]>
---
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/tlb_coalescer.cc
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index f0afd827..cf79b05 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -676,7 +676,7 @@
TranslationState *sender_state =
safe_cast<TranslationState*>(pkt->senderState);
- bool update_stats = !sender_state->prefetch;
+ bool update_stats = !sender_state->isPrefetch;
ThreadContext * tmp_tc = sender_state->tc;
DPRINTF(GPUTLB, "Translation req. for virt. page addr %#x\n",
@@ -891,7 +891,7 @@
safe_cast<TranslationState*>(pkt->senderState);
int req_cnt = tmp_sender_state->reqCnt.back();
- bool update_stats = !tmp_sender_state->prefetch;
+ bool update_stats = !tmp_sender_state->isPrefetch;
if (outcome == TLB_HIT) {
@@ -1102,7 +1102,7 @@
* This feature could be used to explore security issues around
* speculative memory accesses.
*/
- if (!sender_state->prefetch && sender_state->tlbEntry)
+ if (!sender_state->isPrefetch && sender_state->tlbEntry)
pagingProtectionChecks(tc, pkt, local_entry, mode);
int page_size = local_entry->size();
@@ -1124,7 +1124,7 @@
safe_cast<TranslationState*>(pkt->senderState);
ThreadContext *tc = sender_state->tc;
- bool update_stats = !sender_state->prefetch;
+ bool update_stats = !sender_state->isPrefetch;
Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
X86ISA::PageBytes);
@@ -1154,7 +1154,7 @@
// there is a TLB below -> propagate down the TLB hierarchy
tlb->memSidePort[0]->sendFunctional(pkt);
// If no valid translation from a prefetch, then just
return
- if (sender_state->prefetch && !pkt->req->hasPaddr())
+ if (sender_state->isPrefetch && !pkt->req->hasPaddr())
return;
} else {
// Need to access the page table and update the TLB
@@ -1176,7 +1176,7 @@
pte = p->pTable->lookup(vaddr);
}
- if (!sender_state->prefetch) {
+ if (!sender_state->isPrefetch) {
// no PageFaults are permitted after
// the second page table lookup
assert(pte);
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 1df907b..b678f6b 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -293,7 +293,7 @@
*/
TlbEntry *tlbEntry;
// Is this a TLB prefetch request?
- bool prefetch;
+ bool isPrefetch;
// When was the req for this translation issued
uint64_t issueTime;
// Remember where this came from
@@ -307,10 +307,10 @@
Packet::SenderState *saved;
TranslationState(Mode tlb_mode, ThreadContext *_tc,
- bool _prefetch=false,
+ bool is_prefetch=false,
Packet::SenderState *_saved=nullptr)
: tlbMode(tlb_mode), tc(_tc), tlbEntry(nullptr),
- prefetch(_prefetch), issueTime(0),
+ isPrefetch(is_prefetch), issueTime(0),
hitLevel(0),saved(_saved) { }
};
diff --git a/src/gpu-compute/tlb_coalescer.cc
b/src/gpu-compute/tlb_coalescer.cc
index 08f0f95..ea754c1 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -127,7 +127,7 @@
// when we can coalesce a packet update the reqCnt
// that is the number of packets represented by
// this coalesced packet
- if (!incoming_state->prefetch)
+ if (!incoming_state->isPrefetch)
coalesced_state->reqCnt.back() += incoming_state->reqCnt.back();
return true;
@@ -170,7 +170,7 @@
// we are sending the packet back, so pop the reqCnt associated
// with this level in the TLB hiearchy
- if (!sender_state->prefetch)
+ if (!sender_state->isPrefetch)
sender_state->reqCnt.pop_back();
/*
@@ -241,7 +241,7 @@
// push back the port to remember the path back
sender_state->ports.push_back(this);
- bool update_stats = !sender_state->prefetch;
+ bool update_stats = !sender_state->isPrefetch;
if (update_stats) {
// if reqCnt is empty then this packet does not represent
@@ -337,7 +337,7 @@
TheISA::GpuTLB::TranslationState *sender_state =
safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
- bool update_stats = !sender_state->prefetch;
+ bool update_stats = !sender_state->isPrefetch;
if (update_stats)
coalescer->stats.uncoalescedAccesses++;
@@ -461,7 +461,7 @@
safe_cast<TheISA::GpuTLB::TranslationState*>
(first_packet->senderState);
- bool update_stats = !tmp_sender_state->prefetch;
+ bool update_stats = !tmp_sender_state->isPrefetch;
if (update_stats) {
// req_cnt is total number of packets represented
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45409
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4372abb5603eb6a920f7ff127cde54cb24e31377
Gerrit-Change-Number: 45409
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
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