Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45421 )
Change subject: base-stats,misc: Rename Stats namespace as statistics
......................................................................
base-stats,misc: Rename Stats namespace as statistics
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.
::Stats became ::statistics.
"statistics" was chosen over "stats" to avoid generating
conflicts with the already existing variables (there are
way too many "stats" in the codebase), which would make
this patch even more disturbing for the users.
Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Signed-off-by: Daniel R. Carvalho <[email protected]>
---
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/base/stats/hdf5.cc
M src/base/stats/hdf5.hh
M src/base/stats/info.cc
M src/base/stats/info.hh
M src/base/stats/output.hh
M src/base/stats/storage.cc
M src/base/stats/storage.hh
M src/base/stats/storage.test.cc
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/base/stats/types.hh
M src/base/stats/units.hh
M src/base/stats/units.test.cc
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/stats.cc
M src/cpu/minor/stats.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/profile.cc
M src/cpu/simple/exec_context.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
M src/dev/arm/flash_device.cc
M src/dev/arm/flash_device.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/hdlcd.hh
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/smmu_v3_caches.hh
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
M src/dev/net/etherdevice.cc
M src/dev/net/etherdevice.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/exec_stage.cc
M src/gpu-compute/exec_stage.hh
M src/gpu-compute/fetch_stage.cc
M src/gpu-compute/fetch_stage.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.hh
M src/gpu-compute/register_file.cc
M src/gpu-compute/register_file.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/schedule_stage.hh
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/multi.cc
M src/mem/cache/compressors/multi.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/mem_interface.cc
M src/mem/mem_interface.hh
M src/mem/probes/mem_footprint.cc
M src/mem/probes/mem_footprint.hh
M src/mem/probes/stack_dist.cc
M src/mem/probes/stack_dist.hh
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/Router.cc
M src/mem/ruby/network/garnet/Router.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
M src/mem/ruby/network/simple/Throttle.cc
M src/mem/ruby/network/simple/Throttle.hh
M src/mem/ruby/profiler/Profiler.cc
M src/mem/ruby/profiler/Profiler.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/structures/RubyPrefetcher.cc
M src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/TBEStorage.cc
M src/mem/ruby/structures/TBEStorage.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/HTMSequencer.cc
M src/mem/ruby/system/HTMSequencer.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
M src/mem/slicc/symbols/StateMachine.py
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
M src/python/m5/SimObject.py
M src/python/pybind11/stats.cc
M src/sim/clock_domain.cc
M src/sim/clock_domain.hh
M src/sim/dvfs_handler.cc
M src/sim/faults.hh
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/mathexpr_powermodel.hh
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.hh
M src/sim/power_domain.cc
M src/sim/power_domain.hh
M src/sim/power_state.cc
M src/sim/power_state.hh
M src/sim/process.hh
M src/sim/pseudo_inst.cc
M src/sim/root.cc
M src/sim/root.hh
M src/sim/sim_object.cc
M src/sim/sim_object.hh
M src/sim/simulate.cc
M src/sim/stat_control.cc
M src/sim/stat_control.hh
M src/sim/stat_register.cc
M src/sim/stat_register.hh
M src/sim/stats.cc
M src/sim/stats.hh
M src/sim/system.cc
M src/sim/system.hh
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
M src/sim/voltage_domain.cc
M src/sim/voltage_domain.hh
M src/sim/workload.hh
224 files changed, 2,322 insertions(+), 2,227 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Gerrit-Change-Number: 45421
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
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