Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45659 )
Change subject: arch-arm: Fix FEAT_VMID16 for Self Hosted debug
......................................................................
arch-arm: Fix FEAT_VMID16 for Self Hosted debug
The existing code was querying the vmidbits but it was not checking the
VTCR_EL2.VS bit, which dynamically enables/disables VMID16
Signed-off-by: Giacomo Travaglini <[email protected]>
Change-Id: Id1e7df758a636267173c4fcd4db99e5834f21ee9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45659
Reviewed-by: Richard Cooper <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 12 insertions(+), 7 deletions(-)
Approvals:
Richard Cooper: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 5b92fb8..310ccb4 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2021 Arm Limited
* Copyright (c) 2019 Metempsy Technology LSC
* All rights reserved
*
@@ -452,15 +453,18 @@
bool
BrkPoint::testVMIDMatch(ThreadContext *tc)
{
+ const bool vs = ((VTCR_t)(tc->readMiscReg(MISCREG_VTCR_EL2))).vs;
+
uint32_t vmid_index = 55;
- if (VMID16enabled)
+ if (VMID16enabled && vs)
vmid_index = 63;
ExceptionLevel el = currEL(tc);
if (el == EL2)
return false;
- uint32_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index,
48);
- uint32_t v = getVMIDfromReg(tc);
+ vmid_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index, 48);
+ vmid_t v = getVMIDfromReg(tc, vs);
+
return (v == vmid);
}
@@ -520,11 +524,11 @@
return v && SelfDebug::securityStateMatch(tc, ssc, hmc || !aarch32);
}
-uint32_t
-BrkPoint::getVMIDfromReg(ThreadContext *tc)
+vmid_t
+BrkPoint::getVMIDfromReg(ThreadContext *tc, bool vs)
{
uint32_t vmid_index = 39;
- if (VMID16enabled)
+ if (VMID16enabled && vs)
vmid_index = 47;
return bits(tc->readMiscReg(valRegIndex), vmid_index, 32);
}
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 55e74a7..d1db5cc 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2021 Arm Limited
* Copyright (c) 2019 Metempsy Technology LSC
* All rights reserved
*
@@ -103,7 +104,7 @@
}
- inline uint32_t getVMIDfromReg(ThreadContext *tc);
+ vmid_t getVMIDfromReg(ThreadContext *tc, bool vs);
public:
bool testAddrMatch(ThreadContext *tc, Addr pc, uint8_t bas);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id1e7df758a636267173c4fcd4db99e5834f21ee9
Gerrit-Change-Number: 45659
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Richard Cooper <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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