Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45781 )
Change subject: arch-arm: Remove stage2 TLBI flushes from stage1 flushes
......................................................................
arch-arm: Remove stage2 TLBI flushes from stage1 flushes
This is not needed anymore as stage2 flush is now handled by
the MMU. With this patch we are progressively removing any link
between stage1 and stage2 TLBs
Change-Id: I3e9e339a78ac972bc536214152f6c68d6a50cb5c
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/mmu.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
4 files changed, 69 insertions(+), 38 deletions(-)
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 23fd5a2..ab71b00 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -105,8 +105,27 @@
void
flush(const OP &tlbi_op)
{
- getITBPtr()->flush(tlbi_op);
- getDTBPtr()->flush(tlbi_op);
+ flushStage1(tlbi_op);
+
+ if (tlbi_op.stage2Flush()) {
+ flushStage2(tlbi_op.makeStage2());
+ }
+ }
+
+ template <typename OP>
+ void
+ flushStage1(const OP &tlbi_op)
+ {
+ iflush(tlbi_op);
+ dflush(tlbi_op);
+ }
+
+ template <typename OP>
+ void
+ flushStage2(const OP &tlbi_op)
+ {
+ itbStage2->flush(tlbi_op);
+ dtbStage2->flush(tlbi_op);
}
template <typename OP>
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bcc5762..43edddc 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -283,11 +283,6 @@
}
stats.flushTlb++;
-
- // If there's a second stage TLB (and we're not it) then flush it as
well
- if (!isStage2) {
- stage2Tlb->flushAll();
- }
}
void
@@ -312,12 +307,6 @@
}
stats.flushTlb++;
-
- // If there's a second stage TLB (and we're not it) then flush it as
well
- // if we're currently in hyp mode
- if (!isStage2 && isHyp) {
- stage2Tlb->flush(tlbi_op.makeStage2());
- }
}
void
@@ -341,13 +330,6 @@
}
stats.flushTlb++;
-
- // If there's a second stage TLB (and we're not it)
- // and if we're targeting EL1
- // then flush it as well
- if (!isStage2 && tlbi_op.targetEL == EL1) {
- stage2Tlb->flush(tlbi_op.makeStage2());
- }
}
void
@@ -372,12 +354,6 @@
}
stats.flushTlb++;
-
- // If there's a second stage TLB (and we're not it) then flush it as
well
- // if we're currently in hyp mode
- if (!isStage2 && tlbi_op.stage2) {
- stage2Tlb->flush(tlbi_op.makeStage2());
- }
}
void
@@ -403,11 +379,6 @@
}
stats.flushTlb++;
-
- // If there's a second stage TLB (and we're not it) then flush it as
well
- if (!isStage2 && !hyp) {
- stage2Tlb->flush(tlbi_op.makeStage2());
- }
}
void
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index bd784ce..5bcc009 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -48,6 +48,7 @@
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
el2Enabled = EL2Enabled(tc);
+ currentEL = currEL(tc);
getMMUPtr(tc)->flush(*this);
@@ -108,10 +109,10 @@
inHost = (hcr.tge == 1 && hcr.e2h == 1);
el2Enabled = EL2Enabled(tc);
- getMMUPtr(tc)->flush(*this);
+ getMMUPtr(tc)->flushStage1(*this);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getMMUPtr(checker)->flush(*this);
+ getMMUPtr(checker)->flushStage1(*this);
}
}
@@ -145,11 +146,11 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
- getMMUPtr(tc)->flush(*this);
+ getMMUPtr(tc)->flushStage1(*this);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getMMUPtr(checker)->flush(*this);
+ getMMUPtr(checker)->flushStage1(*this);
}
}
@@ -158,11 +159,11 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
- getMMUPtr(tc)->flush(*this);
+ getMMUPtr(tc)->flushStage1(*this);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getMMUPtr(checker)->flush(*this);
+ getMMUPtr(checker)->flushStage1(*this);
}
}
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index ce72dfb..e1825e3 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -72,6 +72,17 @@
(*this)(oc);
}
+ /**
+ * Return true if the TLBI op needs to flush stage2
+ * entries, Defaulting to false in the TLBIOp abstract
+ * class
+ */
+ virtual bool
+ stage2Flush() const
+ {
+ return false;
+ }
+
bool secureLookup;
ExceptionLevel targetEL;
};
@@ -81,11 +92,20 @@
{
public:
TLBIALL(ExceptionLevel _targetEL, bool _secure)
- : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false)
+ : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false),
+ currentEL(EL0)
{}
void operator()(ThreadContext* tc) override;
+ virtual bool
+ stage2Flush() const
+ {
+ // TLBIALL (AArch32) flushing stage2 entries if we're currently
+ // in hyp mode
+ return currentEL == EL2;
+ }
+
TLBIALL
makeStage2() const
{
@@ -94,6 +114,7 @@
bool inHost;
bool el2Enabled;
+ ExceptionLevel currentEL;
};
/** Instruction TLB Invalidate All */
@@ -132,6 +153,13 @@
void operator()(ThreadContext* tc) override;
+ bool
+ stage2Flush() const override
+ {
+ // If we're targeting EL1 then flush stage2 as well
+ return targetEL == EL1;
+ }
+
TLBIALLEL
makeStage2() const
{
@@ -152,6 +180,12 @@
void operator()(ThreadContext* tc) override;
+ bool
+ stage2Flush() const override
+ {
+ return stage2;
+ }
+
TLBIVMALL
makeStage2() const
{
@@ -215,6 +249,12 @@
void operator()(ThreadContext* tc) override;
+ bool
+ stage2Flush() const override
+ {
+ return targetEL != EL2;
+ }
+
TLBIALLN
makeStage2() const
{
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45781
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e9e339a78ac972bc536214152f6c68d6a50cb5c
Gerrit-Change-Number: 45781
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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