Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42102 )
Change subject: cpu: Remove the O3CPU type from the O3CPUImpl.
......................................................................
cpu: Remove the O3CPU type from the O3CPUImpl.
Change-Id: I4dca10ea3ae1c9bb0f2cb55c7d303f1fd8d25283
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42102
Tested-by: kokoro <[email protected]>
Reviewed-by: Nathanael Premillieu <[email protected]>
Maintainer: Gabe Black <[email protected]>
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_state.hh
26 files changed, 81 insertions(+), 100 deletions(-)
Approvals:
Nathanael Premillieu: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index bf0b07c..4c9a7b5 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -87,7 +87,6 @@
{
public:
// Typedefs from the Impl.
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::TimeStruct TimeStruct;
typedef typename Impl::FetchStruct FetchStruct;
typedef typename Impl::IEWStruct IEWStruct;
@@ -136,7 +135,7 @@
public:
/** Construct a DefaultCommit with the given parameters. */
- DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
+ DefaultCommit(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of the DefaultCommit. */
std::string name() const;
@@ -357,7 +356,7 @@
private:
/** Pointer to O3CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Vector of all of the threads. */
std::vector<Thread *> thread;
@@ -480,7 +479,7 @@
struct CommitStats : public Stats::Group
{
- CommitStats(O3CPU *cpu, DefaultCommit *commit);
+ CommitStats(FullO3CPU<Impl> *cpu, DefaultCommit *commit);
/** Stat for the total number of squashed instructions discarded by
* commit.
*/
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 06694bf..4442eb9 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -79,7 +79,8 @@
}
template <class Impl>
-DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams
¶ms)
+DefaultCommit<Impl>::DefaultCommit(FullO3CPU<Impl> *_cpu,
+ const DerivO3CPUParams ¶ms)
: commitPolicy(params.smtCommitPolicy),
cpu(_cpu),
iewToCommitDelay(params.iewToCommitDelay),
@@ -150,7 +151,7 @@
}
template <class Impl>
-DefaultCommit<Impl>::CommitStats::CommitStats(O3CPU *cpu,
+DefaultCommit<Impl>::CommitStats::CommitStats(FullO3CPU<Impl> *cpu,
DefaultCommit *commit)
: Stats::Group(cpu, "commit"),
ADD_STAT(commitSquashedInsts, Stats::Units::Count::get(),
@@ -344,7 +345,7 @@
// Commit must broadcast the number of free entries it has at the
// start of the simulation, so it starts as active.
- cpu->activateStage(O3CPU::CommitIdx);
+ cpu->activateStage(FullO3CPU<Impl>::CommitIdx);
cpu->activityThisCycle();
}
@@ -496,10 +497,10 @@
if (_nextStatus == Inactive && _status == Active) {
DPRINTF(Activity, "Deactivating stage.\n");
- cpu->deactivateStage(O3CPU::CommitIdx);
+ cpu->deactivateStage(FullO3CPU<Impl>::CommitIdx);
} else if (_nextStatus == Active && _status == Inactive) {
DPRINTF(Activity, "Activating stage.\n");
- cpu->activateStage(O3CPU::CommitIdx);
+ cpu->activateStage(FullO3CPU<Impl>::CommitIdx);
}
_status = _nextStatus;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 1ed725b..07e0893 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -315,7 +315,7 @@
DPRINTF(O3CPU, "Workload[%i] process is %#x",
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
- (typename Impl::O3CPU *)(this),
+ (FullO3CPU *)(this),
tid, params.workload[tid]);
//usedTids[tid] = true;
@@ -326,8 +326,7 @@
Process* dummy_proc = NULL;
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
- (typename Impl::O3CPU *)(this),
- tid, dummy_proc);
+ this, tid, dummy_proc);
//usedTids[tid] = false;
}
}
@@ -346,8 +345,7 @@
o3_tc, this->checker);
}
- o3_tc->cpu = (typename Impl::O3CPU *)(this);
- assert(o3_tc->cpu);
+ o3_tc->cpu = this;
o3_tc->thread = this->thread[tid];
// Give the thread the TC.
@@ -391,8 +389,7 @@
}
template <class Impl>
-FullO3CPU<Impl>::
-FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
+FullO3CPU<Impl>::FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
: Stats::Group(cpu),
ADD_STAT(timesIdled, Stats::Units::Count::get(),
"Number of times that the entire CPU went into an idle
state "
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index fbf402e..2eeedea 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -101,8 +101,6 @@
{
public:
// Typedefs from the Impl here.
- typedef typename Impl::O3CPU O3CPU;
-
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 38ba0a6..1d9e04e 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -50,6 +50,9 @@
struct DerivO3CPUParams;
+template <class Impl>
+class FullO3CPU;
+
/**
* DefaultDecode class handles both single threaded and SMT
* decode. Its width is specified by the parameters; each cycles it
@@ -62,7 +65,6 @@
{
private:
// Typedefs from the Impl.
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::FetchStruct FetchStruct;
typedef typename Impl::DecodeStruct DecodeStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -97,7 +99,7 @@
public:
/** DefaultDecode constructor. */
- DefaultDecode(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
+ DefaultDecode(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms);
void startupStage();
@@ -204,7 +206,7 @@
private:
// Interfaces to objects outside of decode.
/** CPU interface. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
@@ -295,7 +297,7 @@
struct DecodeStats : public Stats::Group
{
- DecodeStats(O3CPU *cpu);
+ DecodeStats(FullO3CPU<Impl> *cpu);
/** Stat for total number of idle cycles. */
Stats::Scalar idleCycles;
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index bfbf98f..fc03145 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -59,7 +59,8 @@
using std::list;
template<class Impl>
-DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, const DerivO3CPUParams
¶ms)
+DefaultDecode<Impl>::DefaultDecode(FullO3CPU<Impl> *_cpu,
+ const DerivO3CPUParams ¶ms)
: cpu(_cpu),
renameToDecodeDelay(params.renameToDecodeDelay),
iewToDecodeDelay(params.iewToDecodeDelay),
@@ -122,7 +123,7 @@
}
template <class Impl>
-DefaultDecode<Impl>::DecodeStats::DecodeStats(O3CPU *cpu)
+DefaultDecode<Impl>::DecodeStats::DecodeStats(FullO3CPU<Impl> *cpu)
: Stats::Group(cpu, "decode"),
ADD_STAT(idleCycles, Stats::Units::Cycle::get(),
"Number of cycles decode is idle"),
@@ -457,7 +458,7 @@
DPRINTF(Activity, "Activating stage.\n");
- cpu->activateStage(O3CPU::DecodeIdx);
+ cpu->activateStage(FullO3CPU<Impl>::DecodeIdx);
}
} else {
// If it's not unblocking, then decode will not have any internal
@@ -466,7 +467,7 @@
_status = Inactive;
DPRINTF(Activity, "Deactivating stage.\n");
- cpu->deactivateStage(O3CPU::DecodeIdx);
+ cpu->deactivateStage(FullO3CPU<Impl>::DecodeIdx);
}
}
}
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index dee344b..2b9e2de 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -73,7 +73,6 @@
{
public:
/** Typedefs from Impl. */
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::FetchStruct FetchStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -212,7 +211,7 @@
public:
/** DefaultFetch constructor. */
- DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
+ DefaultFetch(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of fetch. */
std::string name() const;
@@ -402,7 +401,7 @@
private:
/** Pointer to the O3CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
@@ -544,7 +543,7 @@
protected:
struct FetchStatGroup : public Stats::Group
{
- FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch);
+ FetchStatGroup(FullO3CPU<Impl> *cpu, DefaultFetch *fetch);
// @todo: Consider making these
// vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss.
*/
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 587ae1a..a5627e1 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -73,7 +73,8 @@
#include "sim/system.hh"
template<class Impl>
-DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams
¶ms)
+DefaultFetch<Impl>::DefaultFetch(FullO3CPU<Impl> *_cpu,
+ const DerivO3CPUParams ¶ms)
: fetchPolicy(params.smtFetchPolicy),
cpu(_cpu),
branchPred(nullptr),
@@ -158,7 +159,7 @@
template <class Impl>
DefaultFetch<Impl>::
-FetchStatGroup::FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch)
+FetchStatGroup::FetchStatGroup(FullO3CPU<Impl> *cpu, DefaultFetch *fetch)
: Stats::Group(cpu, "fetch"),
ADD_STAT(icacheStallCycles, Stats::Units::Cycle::get(),
"Number of cycles fetch is stalled on an Icache miss"),
@@ -493,7 +494,7 @@
if (_status == Inactive) {
DPRINTF(Activity, "Activating stage.\n");
- cpu->activateStage(O3CPU::FetchIdx);
+ cpu->activateStage(FullO3CPU<Impl>::FetchIdx);
_status = Active;
}
@@ -506,7 +507,7 @@
if (_status == Active) {
DPRINTF(Activity, "Deactivating stage.\n");
- cpu->deactivateStage(O3CPU::FetchIdx);
+ cpu->deactivateStage(FullO3CPU<Impl>::FetchIdx);
_status = Inactive;
}
@@ -831,7 +832,7 @@
"completion\n",tid);
}
- cpu->activateStage(O3CPU::FetchIdx);
+ cpu->activateStage(FullO3CPU<Impl>::FetchIdx);
}
return Active;
@@ -842,7 +843,7 @@
if (_status == Active) {
DPRINTF(Activity, "Deactivating stage.\n");
- cpu->deactivateStage(O3CPU::FetchIdx);
+ cpu->deactivateStage(FullO3CPU<Impl>::FetchIdx);
}
return Inactive;
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 4afee5b..a0f4869 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -82,7 +82,6 @@
{
private:
//Typedefs from Impl
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::TimeStruct TimeStruct;
typedef typename Impl::IEWStruct IEWStruct;
typedef typename Impl::RenameStruct RenameStruct;
@@ -129,7 +128,7 @@
public:
/** Constructs a DefaultIEW with the given parameters. */
- DefaultIEW(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
+ DefaultIEW(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of the DefaultIEW stage. */
std::string name() const;
@@ -347,7 +346,7 @@
private:
/** CPU pointer. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Records if IEW has written to the time buffer this cycle, so that
the
* CPU can deschedule itself if there is no activity.
@@ -424,7 +423,7 @@
struct IEWStats : public Stats::Group
{
- IEWStats(O3CPU *cpu);
+ IEWStats(FullO3CPU<Impl> *cpu);
/** Stat for total number of idle cycles. */
Stats::Scalar idleCycles;
@@ -460,7 +459,7 @@
struct ExecutedInstStats : public Stats::Group
{
- ExecutedInstStats(O3CPU* cpu);
+ ExecutedInstStats(FullO3CPU<Impl> *cpu);
/** Stat for total number of executed instructions. */
Stats::Scalar numInsts;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 7c6fe5a..54327fa 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -62,7 +62,8 @@
#include "params/DerivO3CPU.hh"
template<class Impl>
-DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
+DefaultIEW<Impl>::DefaultIEW(FullO3CPU<Impl> *_cpu,
+ const DerivO3CPUParams ¶ms)
: issueToExecQueue(params.backComSize, params.forwardComSize),
cpu(_cpu),
instQueue(_cpu, this, params),
@@ -142,8 +143,7 @@
}
template <class Impl>
-DefaultIEW<Impl>::
-IEWStats::IEWStats(O3CPU *cpu)
+DefaultIEW<Impl>::IEWStats::IEWStats(FullO3CPU<Impl> *cpu)
: Stats::Group(cpu),
ADD_STAT(idleCycles, Stats::Units::Cycle::get(),
"Number of cycles IEW is idle"),
@@ -218,8 +218,8 @@
}
template <class Impl>
-DefaultIEW<Impl>::IEWStats::
-ExecutedInstStats::ExecutedInstStats(O3CPU *cpu)
+DefaultIEW<Impl>::IEWStats::ExecutedInstStats::ExecutedInstStats(
+ FullO3CPU<Impl> *cpu)
: Stats::Group(cpu),
ADD_STAT(numInsts, Stats::Units::Count::get(),
"Number of executed instructions"),
@@ -288,7 +288,7 @@
cpu->checker->setDcachePort(&ldstQueue.getDataPort());
}
- cpu->activateStage(O3CPU::IEWIdx);
+ cpu->activateStage(FullO3CPU<Impl>::IEWIdx);
}
template<class Impl>
@@ -865,7 +865,7 @@
DefaultIEW<Impl>::activateStage()
{
DPRINTF(Activity, "Activating stage.\n");
- cpu->activateStage(O3CPU::IEWIdx);
+ cpu->activateStage(FullO3CPU<Impl>::IEWIdx);
}
template <class Impl>
@@ -873,7 +873,7 @@
DefaultIEW<Impl>::deactivateStage()
{
DPRINTF(Activity, "Deactivating stage.\n");
- cpu->deactivateStage(O3CPU::IEWIdx);
+ cpu->deactivateStage(FullO3CPU<Impl>::IEWIdx);
}
template<class Impl>
diff --git a/src/cpu/o3/impl.hh b/src/cpu/o3/impl.hh
index 2c7242e..d9d3e1f 100644
--- a/src/cpu/o3/impl.hh
+++ b/src/cpu/o3/impl.hh
@@ -31,10 +31,6 @@
#include "cpu/o3/comm.hh"
-// Forward declarations.
-template <class Impl>
-class FullO3CPU;
-
/** Implementation specific struct that defines several key types to the
* CPU, the stages within the CPU, the time buffers, and the DynInst.
* The struct defines the ISA, the CPU policy, the specific DynInst, the
@@ -62,16 +58,6 @@
/** The struct for all backwards communication. */
typedef TimeBufStruct<O3CPUImpl> TimeStruct;
-
-
- /** The O3CPU type to be used. */
- typedef FullO3CPU<O3CPUImpl> O3CPU;
-
- /** Same typedef, but for CPUType. BaseDynInst may not always use
- * an O3 CPU, so it's clearer to call it CPUType instead in that
- * case.
- */
- typedef O3CPU CPUType;
};
#endif // __CPU_O3_SPARC_IMPL_HH__
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 6c85ffd..879655d 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -67,6 +67,9 @@
template <class Impl>
class DefaultIEW;
+template <class Impl>
+class FullO3CPU;
+
/**
* A standard instruction queue class. It holds ready instructions, in
* order, in seperate priority queues to facilitate the scheduling of
@@ -89,7 +92,6 @@
{
public:
//Typedefs from the Impl.
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::IssueStruct IssueStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -125,7 +127,7 @@
};
/** Constructs an IQ. */
- InstructionQueue(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+ InstructionQueue(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams ¶ms);
/** Destructs the IQ. */
@@ -282,7 +284,7 @@
/////////////////////////
/** Pointer to the CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Cache interface. */
MemInterface *dcacheInterface;
@@ -479,7 +481,7 @@
struct IQStats : public Stats::Group
{
- IQStats(O3CPU *cpu, const unsigned &total_width);
+ IQStats(FullO3CPU<Impl> *cpu, const unsigned &total_width);
/** Stat for number of instructions added. */
Stats::Scalar instsAdded;
/** Stat for number of non-speculative instructions added. */
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 9373f6b..3159742 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -84,7 +84,7 @@
}
template <class Impl>
-InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr,
+InstructionQueue<Impl>::InstructionQueue(FullO3CPU<Impl> *cpu_ptr,
DefaultIEW<Impl> *iew_ptr, const DerivO3CPUParams ¶ms)
: cpu(cpu_ptr),
iewStage(iew_ptr),
@@ -177,7 +177,7 @@
template <class Impl>
InstructionQueue<Impl>::
-IQStats::IQStats(O3CPU *cpu, const unsigned &total_width)
+IQStats::IQStats(FullO3CPU<Impl> *cpu, const unsigned &total_width)
: Stats::Group(cpu),
ADD_STAT(instsAdded, Stats::Units::Count::get(),
"Number of instructions added to the IQ (excludes non-spec)"),
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index eb76e65..021bab5 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -75,8 +75,6 @@
class LSQ
{
public:
- typedef typename Impl::O3CPU O3CPU;
-
class LSQRequest;
/** Derived class to hold any sender state the LSQ needs. */
class LSQSenderState : public Packet::SenderState
@@ -794,7 +792,7 @@
};
/** Constructs an LSQ with the given parameters. */
- LSQ(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+ LSQ(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams ¶ms);
~LSQ() { }
@@ -1051,7 +1049,7 @@
const std::vector<bool>& byte_enable);
/** The CPU pointer. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** The IEW stage pointer. */
DefaultIEW<Impl> *iewStage;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 5cde78e..bb53bb6 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -68,7 +68,7 @@
}
template <class Impl>
-LSQ<Impl>::LSQ(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+LSQ<Impl>::LSQ(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams ¶ms)
: cpu(cpu_ptr), iewStage(iew_ptr),
_cacheBlocked(false),
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 4d3c419..14768f8 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -85,7 +85,6 @@
public:
static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::IssueStruct IssueStruct;
using LSQSenderState = typename LSQ<Impl>::LSQSenderState;
@@ -225,7 +224,7 @@
}
/** Initializes the LSQ unit with the specified number of entries. */
- void init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+ void init(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams ¶ms, LSQ<Impl> *lsq_ptr, unsigned
id);
/** Returns the name of the LSQ unit. */
@@ -398,7 +397,7 @@
private:
/** Pointer to the CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Pointer to the IEW stage. */
DefaultIEW<Impl> *iewStage;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 174916d..df789ce 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -215,7 +215,7 @@
template<class Impl>
void
-LSQUnit<Impl>::init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
+LSQUnit<Impl>::init(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams ¶ms, LSQ<Impl> *lsq_ptr, unsigned id)
{
lsqID = id;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index b2cf9bf..3874e5f 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -68,6 +68,9 @@
template <class Impl>
class InstructionQueue;
+template <class Impl>
+class FullO3CPU;
+
/**
* Memory dependency unit class. This holds the memory dependence
predictor.
* As memory operations are issued to the IQ, they are also issued to this
@@ -86,8 +89,6 @@
std::string _name;
public:
- typedef typename Impl::O3CPU O3CPU;
-
/** Empty constructor. Must call init() prior to using in this case. */
MemDepUnit();
@@ -101,7 +102,8 @@
std::string name() const { return _name; }
/** Initializes the unit with parameters and a thread id. */
- void init(const DerivO3CPUParams ¶ms, ThreadID tid, O3CPU *cpu);
+ void init(const DerivO3CPUParams ¶ms, ThreadID tid,
+ FullO3CPU<Impl> *cpu);
/** Determine if we are drained. */
bool isDrained() const;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index 34bba53..ce1aa26 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -99,7 +99,7 @@
template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::init(
- const DerivO3CPUParams ¶ms, ThreadID tid, O3CPU *cpu)
+ const DerivO3CPUParams ¶ms, ThreadID tid, FullO3CPU<Impl> *cpu)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
diff --git a/src/cpu/o3/probe/elastic_trace.hh
b/src/cpu/o3/probe/elastic_trace.hh
index 70f2763..914e4ea 100644
--- a/src/cpu/o3/probe/elastic_trace.hh
+++ b/src/cpu/o3/probe/elastic_trace.hh
@@ -60,6 +60,9 @@
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
+template <class Impl>
+class FullO3CPU;
+
/**
* The elastic trace is a type of probe listener and listens to probe
points
* in multiple stages of the O3CPU. The notify method is called on a probe
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index 2c4796a..0fa8f18 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -74,7 +74,6 @@
{
public:
// Typedefs from the Impl.
- typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DecodeStruct DecodeStruct;
typedef typename Impl::RenameStruct RenameStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -126,7 +125,7 @@
public:
/** DefaultRename constructor. */
- DefaultRename(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
+ DefaultRename(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of rename. */
std::string name() const;
@@ -320,7 +319,7 @@
std::list<RenameHistory> historyBuffer[O3MaxThreads];
/** Pointer to CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Pointer to main time buffer used for backwards communication. */
TimeBuffer<TimeStruct> *timeBuffer;
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index bc33c5d..1a5409b 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -53,7 +53,8 @@
#include "params/DerivO3CPU.hh"
template <class Impl>
-DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, const DerivO3CPUParams
¶ms)
+DefaultRename<Impl>::DefaultRename(FullO3CPU<Impl> *_cpu,
+ const DerivO3CPUParams ¶ms)
: cpu(_cpu),
iewToRenameDelay(params.iewToRenameDelay),
decodeToRenameDelay(params.decodeToRenameDelay),
@@ -865,7 +866,7 @@
DPRINTF(Activity, "Activating stage.\n");
- cpu->activateStage(O3CPU::RenameIdx);
+ cpu->activateStage(FullO3CPU<Impl>::RenameIdx);
}
} else {
// If it's not unblocking, then rename will not have any internal
@@ -874,7 +875,7 @@
_status = Inactive;
DPRINTF(Activity, "Deactivating stage.\n");
- cpu->deactivateStage(O3CPU::RenameIdx);
+ cpu->deactivateStage(FullO3CPU<Impl>::RenameIdx);
}
}
}
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index 1259b53..155352a 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -58,9 +58,6 @@
class ROB
{
public:
- //Typedefs from the Impl.
- typedef typename Impl::O3CPU O3CPU;
-
typedef std::pair<RegIndex, RegIndex> UnmapInfo;
typedef typename std::list<O3DynInstPtr>::iterator InstIt;
@@ -84,7 +81,7 @@
* @param _cpu The cpu object pointer.
* @param params The cpu params including several ROB-specific
parameters.
*/
- ROB(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
+ ROB(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms);
std::string name() const;
@@ -261,7 +258,7 @@
void resetState();
/** Pointer to the CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
/** Active Threads in CPU */
std::list<ThreadID> *activeThreads;
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 6bdf23a..c48484c 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -51,7 +51,7 @@
#include "params/DerivO3CPU.hh"
template <class Impl>
-ROB<Impl>::ROB(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
+ROB<Impl>::ROB(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams ¶ms)
: robPolicy(params.smtROBPolicy),
cpu(_cpu),
numEntries(params.numROBEntries),
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 8dd4165..5a63641 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -63,10 +63,8 @@
class O3ThreadContext : public ThreadContext
{
public:
- typedef typename Impl::O3CPU O3CPU;
-
/** Pointer to the CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
bool
schedule(PCEvent *e) override
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 03091c7..68d689e 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -64,11 +64,10 @@
struct O3ThreadState : public ThreadState
{
typedef ThreadContext::Status Status;
- typedef typename Impl::O3CPU O3CPU;
private:
/** Pointer to the CPU. */
- O3CPU *cpu;
+ FullO3CPU<Impl> *cpu;
public:
PCEventQueue pcEventQueue;
@@ -96,7 +95,7 @@
/** Pointer to the hardware transactional memory checkpoint. */
std::unique_ptr<BaseHTMCheckpoint> htmCheckpoint;
- O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
+ O3ThreadState(FullO3CPU<Impl> *_cpu, int _thread_num, Process
*_process)
: ThreadState(_cpu, _thread_num, _process), cpu(_cpu),
comInstEventQueue("instruction-based event queue"),
noSquashFromTC(false), trapPending(false), tc(nullptr)
17 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42102
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4dca10ea3ae1c9bb0f2cb55c7d303f1fd8d25283
Gerrit-Change-Number: 42102
Gerrit-PatchSet: 20
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Nathanael Premillieu <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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