Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45438 )
Change subject: mem: Rename "memory" variables as "mem"
......................................................................
mem: Rename "memory" variables as "mem"
Pave the way to a "memory" namespace by renaming all
the variables that have a naming conflict.
Change-Id: I8327256ed88f1791225fe158f023132850303472
Signed-off-by: Daniel R. Carvalho <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45438
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/semihosting.cc
M src/mem/cfi_mem.cc
M src/mem/cfi_mem.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/sim/system.cc
12 files changed, 43 insertions(+), 43 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 13038f0..91a6205 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -553,9 +553,9 @@
fatal_if(memories.size() < 1, "No memories reported from System");
warn_if(memories.size() > 1, "Multiple physical memory ranges
available. "
"Using first range heap/stack.");
- const AddrRange memory = *memories.begin();
- const Addr mem_start = memory.start() + memReserve;
- Addr mem_end = memory.end();
+ const AddrRange mem = *memories.begin();
+ const Addr mem_start = mem.start() + memReserve;
+ Addr mem_end = mem.end();
// Make sure that 32-bit guests can access their memory.
if (!aarch64) {
diff --git a/src/mem/cfi_mem.cc b/src/mem/cfi_mem.cc
index 0bcb180..de1348e 100644
--- a/src/mem/cfi_mem.cc
+++ b/src/mem/cfi_mem.cc
@@ -447,46 +447,46 @@
CfiMemory::MemoryPort::MemoryPort(const std::string& _name,
CfiMemory& _memory)
- : ResponsePort(_name, &_memory), memory(_memory)
+ : ResponsePort(_name, &_memory), mem(_memory)
{ }
AddrRangeList
CfiMemory::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
- ranges.push_back(memory.getAddrRange());
+ ranges.push_back(mem.getAddrRange());
return ranges;
}
Tick
CfiMemory::MemoryPort::recvAtomic(PacketPtr pkt)
{
- return memory.recvAtomic(pkt);
+ return mem.recvAtomic(pkt);
}
Tick
CfiMemory::MemoryPort::recvAtomicBackdoor(
PacketPtr pkt, MemBackdoorPtr &_backdoor)
{
- return memory.recvAtomicBackdoor(pkt, _backdoor);
+ return mem.recvAtomicBackdoor(pkt, _backdoor);
}
void
CfiMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
- memory.recvFunctional(pkt);
+ mem.recvFunctional(pkt);
}
bool
CfiMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
{
- return memory.recvTimingReq(pkt);
+ return mem.recvTimingReq(pkt);
}
void
CfiMemory::MemoryPort::recvRespRetry()
{
- memory.recvRespRetry();
+ mem.recvRespRetry();
}
void
diff --git a/src/mem/cfi_mem.hh b/src/mem/cfi_mem.hh
index f2c65d3..e49a154 100644
--- a/src/mem/cfi_mem.hh
+++ b/src/mem/cfi_mem.hh
@@ -232,7 +232,7 @@
class MemoryPort : public ResponsePort
{
private:
- CfiMemory& memory;
+ CfiMemory& mem;
public:
MemoryPort(const std::string& _name, CfiMemory& _memory);
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index 98bc70f..c4ca097 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -353,38 +353,38 @@
DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
DRAMSim2& _memory)
- : ResponsePort(_name, &_memory), memory(_memory)
+ : ResponsePort(_name, &_memory), mem(_memory)
{ }
AddrRangeList
DRAMSim2::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
- ranges.push_back(memory.getAddrRange());
+ ranges.push_back(mem.getAddrRange());
return ranges;
}
Tick
DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
{
- return memory.recvAtomic(pkt);
+ return mem.recvAtomic(pkt);
}
void
DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
{
- memory.recvFunctional(pkt);
+ mem.recvFunctional(pkt);
}
bool
DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
{
// pass it to the memory controller
- return memory.recvTimingReq(pkt);
+ return mem.recvTimingReq(pkt);
}
void
DRAMSim2::MemoryPort::recvRespRetry()
{
- memory.recvRespRetry();
+ mem.recvRespRetry();
}
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index a417c07..f3792ae 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -64,7 +64,7 @@
private:
- DRAMSim2& memory;
+ DRAMSim2& mem;
public:
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index 480da7f..0027a85 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -351,38 +351,38 @@
DRAMsim3::MemoryPort::MemoryPort(const std::string& _name,
DRAMsim3& _memory)
- : ResponsePort(_name, &_memory), memory(_memory)
+ : ResponsePort(_name, &_memory), mem(_memory)
{ }
AddrRangeList
DRAMsim3::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
- ranges.push_back(memory.getAddrRange());
+ ranges.push_back(mem.getAddrRange());
return ranges;
}
Tick
DRAMsim3::MemoryPort::recvAtomic(PacketPtr pkt)
{
- return memory.recvAtomic(pkt);
+ return mem.recvAtomic(pkt);
}
void
DRAMsim3::MemoryPort::recvFunctional(PacketPtr pkt)
{
- memory.recvFunctional(pkt);
+ mem.recvFunctional(pkt);
}
bool
DRAMsim3::MemoryPort::recvTimingReq(PacketPtr pkt)
{
// pass it to the memory controller
- return memory.recvTimingReq(pkt);
+ return mem.recvTimingReq(pkt);
}
void
DRAMsim3::MemoryPort::recvRespRetry()
{
- memory.recvRespRetry();
+ mem.recvRespRetry();
}
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index f667c4d..ca34d6d 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -66,7 +66,7 @@
private:
- DRAMsim3& memory;
+ DRAMsim3& mem;
public:
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index fb50e67..98a5e3f 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -348,33 +348,33 @@
MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n,
MemSinkCtrl& m)
: QueuedResponsePort(n, &m, queue, true),
- memory(m), queue(memory, *this, true)
+ mem(m), queue(mem, *this, true)
{}
AddrRangeList
MemSinkCtrl::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
- ranges.push_back(memory.interface->getAddrRange());
+ ranges.push_back(mem.interface->getAddrRange());
return ranges;
}
Tick
MemSinkCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
{
- return memory.recvAtomic(pkt);
+ return mem.recvAtomic(pkt);
}
void
MemSinkCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
{
- pkt->pushLabel(memory.name());
+ pkt->pushLabel(mem.name());
if (!queue.trySatisfyFunctional(pkt)) {
// Default implementation of SimpleTimingPort::recvFunctional()
// calls recvAtomic() and throws away the latency; we can save a
// little here by just not calculating the latency.
- memory.recvFunctional(pkt);
+ mem.recvFunctional(pkt);
}
pkt->popLabel();
@@ -383,7 +383,7 @@
bool
MemSinkCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
{
- return memory.recvTimingReq(pkt);
+ return mem.recvTimingReq(pkt);
}
} // namespace qos
diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 4946115..3c229ec 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -79,7 +79,7 @@
{
private:
/** reference to parent memory object */
- MemSinkCtrl& memory;
+ MemSinkCtrl& mem;
/** Outgoing packet responses queue */
RespPacketQueue queue;
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 327a326..332ee5b 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -258,44 +258,44 @@
SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
SimpleMemory& _memory)
- : ResponsePort(_name, &_memory), memory(_memory)
+ : ResponsePort(_name, &_memory), mem(_memory)
{ }
AddrRangeList
SimpleMemory::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
- ranges.push_back(memory.getAddrRange());
+ ranges.push_back(mem.getAddrRange());
return ranges;
}
Tick
SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
{
- return memory.recvAtomic(pkt);
+ return mem.recvAtomic(pkt);
}
Tick
SimpleMemory::MemoryPort::recvAtomicBackdoor(
PacketPtr pkt, MemBackdoorPtr &_backdoor)
{
- return memory.recvAtomicBackdoor(pkt, _backdoor);
+ return mem.recvAtomicBackdoor(pkt, _backdoor);
}
void
SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
- memory.recvFunctional(pkt);
+ mem.recvFunctional(pkt);
}
bool
SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
{
- return memory.recvTimingReq(pkt);
+ return mem.recvTimingReq(pkt);
}
void
SimpleMemory::MemoryPort::recvRespRetry()
{
- memory.recvRespRetry();
+ mem.recvRespRetry();
}
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 22b2323..716bd41 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -82,7 +82,7 @@
class MemoryPort : public ResponsePort
{
private:
- SimpleMemory& memory;
+ SimpleMemory& mem;
public:
MemoryPort(const std::string& _name, SimpleMemory& _memory);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 2726663..57ae62f 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -226,9 +226,9 @@
if (!FullSystem) {
AddrRangeList memories = physmem.getConfAddrRanges();
assert(!memories.empty());
- for (const auto &memory : memories) {
- assert(!memory.interleaved());
- memPools.emplace_back(this, memory.start(), memory.end());
+ for (const auto &mem : memories) {
+ assert(!mem.interleaved());
+ memPools.emplace_back(this, mem.start(), mem.end());
}
/*
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8327256ed88f1791225fe158f023132850303472
Gerrit-Change-Number: 45438
Gerrit-PatchSet: 10
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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