Arthur Perais has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46299 )
Change subject: arch-arm: Annotate zero-idiom instructions in ISA parser
......................................................................
arch-arm: Annotate zero-idiom instructions in ISA parser
Several Aarch64 instructions are zero-idioms (e.g., eor x0, x1, x1).
This patch annotates the most obvious ones and introduces the
isZeroIdiom() API on StaticInst and DynInst.
Detected idioms are :
and dst, src, 0x0
and dst, xzr, src
and dst, src, xzr
eor dst, src1, src2 with src1 == src2 and src2 not a shifted/extended
register
movz dst, 0x0
CPU may then use this information to perform zero-idiom elimination
at Rename, for instance.
Change-Id: Ib9399f064b9f29f4653c3684b75d19973fcccfd6
---
M src/arch/arm/isa/insts/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/isa_parser/isa_parser.py
M src/cpu/StaticInstFlags.py
M src/cpu/o3/dyn_inst.hh
M src/cpu/static_inst.hh
6 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/isa/insts/aarch64.isa
b/src/arch/arm/isa/insts/aarch64.isa
index fbedf89..1eb328e 100644
--- a/src/arch/arm/isa/insts/aarch64.isa
+++ b/src/arch/arm/isa/insts/aarch64.isa
@@ -36,8 +36,12 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
let {{
- movzCode = 'Dest64 = ((uint64_t)imm1) << imm2;'
- movzIop = ArmInstObjParams("movz", "Movz", "RegImmImmOp", movzCode, [])
+ snippet_movz = {}
+ snippet_movz['code'] = 'Dest64 = ((uint64_t)imm1) << imm2;'
+ snippet_movz['constructor_opt'] = '''
+ flags[IsZeroIdiom] = (_imm1 == 0x0);
+ '''
+ movzIop = ArmInstObjParams("movz", "Movz", "RegImmImmOp",
snippet_movz, [])
header_output += RegImmImmOpDeclare.subst(movzIop)
decoder_output += RegImmImmOpConstructor.subst(movzIop)
exec_output += BasicExecute.subst(movzIop)
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 11df936..8dc05ed 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -96,7 +96,30 @@
''' + code
ccCode = createCcCode64(carryCode64[flagType],
overflowCode64[flagType])
Name = mnem.capitalize() + suffix
- iop = ArmInstObjParams(mnem, Name, base, code)
+
+ snippet_mnem = {}
+ snippet_mnem['code'] = code
+
+ if mnem == 'and':
+ if base == 'DataXImmOp':
+ # and rd, rs1, 0x0
+ snippet_mnem['constructor_opt'] = '''
+ flags[IsZeroIdiom] = _imm == 0x0;
+ '''
+ else:
+ # and rd, rs1, xzr
+ # and rd, xzr, rs2
+ snippet_mnem['constructor_opt'] = '''
+ flags[IsZeroIdiom] = (_op1 == 31) || (_op2 == 31);
+ '''
+ elif mnem == 'eor':
+ # eor rd, rs1, rs2 with rs1 == rs2
+ if base == 'DataXSRegOp':
+ snippet_mnem['constructor_opt'] = '''
+ flags[IsZeroIdiom] = (_op1 == _op2) && (_shiftAmt == 0);
+ '''
+
+ iop = ArmInstObjParams(mnem, Name, base, snippet_mnem)
iopCc = ArmInstObjParams(mnem + "s", Name + "Cc", base, code +
ccCode)
def subst(iop):
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index bfe9c91..6764af1 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -410,6 +410,9 @@
self.constructor = header + \
self.operands.concatAttrStrings('constructor')
+ if 'constructor_opt' in snippets.keys():
+ self.constructor = self.constructor +
snippets['constructor_opt']
+
self.flags = self.operands.concatAttrLists('flags')
self.op_class = None
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 4775289..a74198e 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -68,6 +68,10 @@
'IsCall', # Subroutine call.
'IsReturn', # Subroutine return.
+ ## Rename-optimizations
+
+ 'IsZeroIdiom', # Is the instruction always producing 0x0
+
'IsSerializing', # Serializes pipeline: won't execute until all
# older instructions have committed.
'IsSerializeBefore',
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 24665a5..f1531d8 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -597,6 +597,7 @@
bool isControl() const { return staticInst->isControl(); }
bool isCall() const { return staticInst->isCall(); }
bool isReturn() const { return staticInst->isReturn(); }
+ bool isZeroIdiom() const { return staticInst->isZeroIdiom(); }
bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
bool isCondCtrl() const { return staticInst->isCondCtrl(); }
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 2af6a0b..3a65bcb 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -179,6 +179,7 @@
bool isControl() const { return flags[IsControl]; }
bool isCall() const { return flags[IsCall]; }
bool isReturn() const { return flags[IsReturn]; }
+ bool isZeroIdiom() const { return flags[IsZeroIdiom]; }
bool isDirectCtrl() const { return flags[IsDirectControl]; }
bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
bool isCondCtrl() const { return flags[IsCondControl]; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib9399f064b9f29f4653c3684b75d19973fcccfd6
Gerrit-Change-Number: 46299
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Perais <arthurper...@gmail.com>
Gerrit-MessageType: newchange
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