Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45920 )
Change subject: arch-riscv: Update the way a valid virtual address is
computed
......................................................................
arch-riscv: Update the way a valid virtual address is computed
According to privileged ISA specs, a valid 64 bit virtual address should
have bit 63-39 same as bit 38 (for Sv39). Without this change, kernel page
fault handler does not seem to work correctly. For example, while running
a program, the kernel was segfaulting complaining that it cannot handle
kernel paging request at some virtual address (which is the faulting
address returned by gem5 currently, with all bits after first 39 cleared).
With this change, that error goes away.
Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45920
Reviewed-by: Jason Lowe-Power <[email protected]>
Reviewed-by: Nils Asmussen <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/tlb.cc
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nils Asmussen: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index d3c3905..8dadd96 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -418,7 +418,7 @@
void
Walker::WalkerState::setupWalk(Addr vaddr)
{
- vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
+ vaddr = Addr(sext<VADDR_BITS>(vaddr));
Addr shift = PageShift + LEVEL_BITS * 2;
Addr idx = (vaddr >> shift) & LEVEL_MASK;
@@ -486,7 +486,7 @@
* well.
*/
Addr vaddr = req->getVaddr();
- vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
+ vaddr = Addr(sext<VADDR_BITS>(vaddr));
Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid,
mode);
req->setPaddr(paddr);
walker->pma->check(req);
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index a5e4107..1ec848e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -277,7 +277,7 @@
{
delayed = false;
- Addr vaddr = req->getVaddr() & ((static_cast<Addr>(1) << VADDR_BITS) -
1);
+ Addr vaddr = Addr(sext<VADDR_BITS>(req->getVaddr()));
SATP satp = tc->readMiscReg(MISCREG_SATP);
TlbEntry *e = lookup(vaddr, satp.asid, mode, false);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45920
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
Gerrit-Change-Number: 45920
Gerrit-PatchSet: 6
Gerrit-Owner: Ayaz Akram <[email protected]>
Gerrit-Reviewer: Ayaz Akram <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Nils Asmussen <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Gabe Black <[email protected]>
Gerrit-MessageType: merged
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