Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46621 )
Change subject: cpu: Fix MMU port addition from the CheckerCPU
......................................................................
cpu: Fix MMU port addition from the CheckerCPU
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I596eb74faa2226e49f195c6c178e296f5eca7d37
---
M src/cpu/BaseCPU.py
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index bd702e2..acd1db1 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -221,7 +221,7 @@
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
- self._cached_ports += [ ".".join("checker", port) \
+ self._cached_ports += [ "checker." + port
for port in ArchMMU.walkerPorts() ]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I596eb74faa2226e49f195c6c178e296f5eca7d37
Gerrit-Change-Number: 46621
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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