Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46979 )
Change subject: mem: add MSHR debuging stats
......................................................................
mem: add MSHR debuging stats
MSHR does not have debug stat.
This commit adds 2 debug flags: MSHREntries and MSHRTargets.
MSHREntries only print the number of used MSHR on
allocation/deallocation of a MSHR.
MSHRTargets is way more verbose and for each allocated/ deallocated
target, it will print all informations about the added/removed target
but also on the MSHR.
In further patches, more information could be added for MSHRTargets,
especially for debugging the interaction between regular targets
and deferred ones.
Change-Id: If9943b9ea57e351060824521f9e25192ab25403a
---
M src/mem/cache/SConscript
M src/mem/cache/base.cc
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
6 files changed, 74 insertions(+), 10 deletions(-)
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index f07a918..2d3d245 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -47,9 +47,14 @@
DebugFlag('CacheVerbose')
DebugFlag('HWPrefetch')
+DebugFlag('MSHREntries')
+DebugFlag('MSHRTargets')
+
+
# CacheTags is so outrageously verbose, printing the cache's entire tag
# array on each timing access, that you should probably have to ask for
# it explicitly even above and beyond CacheAll.
CompoundFlag('CacheAll', ['Cache', 'CacheComp', 'CachePort', 'CacheRepl',
- 'CacheVerbose', 'HWPrefetch'])
+ 'CacheVerbose', 'HWPrefetch',
+ 'MSHREntries', 'MSHRTargets'])
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 928c30b..4aa4f30 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -76,7 +76,7 @@
: ClockedObject(p),
cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
- mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve), // see below
+ mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve, p.name),
writeBuffer("write buffer", p.write_buffers, p.mshrs), // see below
tags(p.tags),
compressor(p.compressor),
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 9dae03d..481a66f 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -53,6 +53,8 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
+#include "debug/MSHREntries.hh"
+#include "debug/MSHRTargets.hh"
#include "mem/cache/base.hh"
#include "mem/request.hh"
#include "sim/core.hh"
@@ -317,6 +319,8 @@
// All targets must refer to the same block
assert(target->matchBlockAddr(targets.front().pkt, blkSize));
+
+ DPRINTF(MSHRTargets, "New target allocated %s", print());
}
@@ -406,6 +410,8 @@
targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
alloc_on_fill);
}
+
+ DPRINTF(MSHRTargets, "New target allocated %s", print());
}
bool
@@ -714,12 +720,12 @@
hasFromCache() ? "HasFromCache" : "");
if (!targets.empty()) {
- ccprintf(os, "%s Targets:\n", prefix);
- targets.print(os, verbosity, prefix + " ");
+ ccprintf(os, "%s Targets:\n", prefix);
+ targets.print(os, verbosity, prefix + " ");
}
if (!deferredTargets.empty()) {
- ccprintf(os, "%s Deferred Targets:\n", prefix);
- deferredTargets.print(os, verbosity, prefix + " ");
+ ccprintf(os, "%s Deferred Targets:\n", prefix);
+ deferredTargets.print(os, verbosity, prefix + " ");
}
}
@@ -731,6 +737,12 @@
return str.str();
}
+std::string
+MSHR::name() const
+{
+ return cacheName;
+}
+
bool
MSHR::matchBlockAddr(const Addr addr, const bool is_secure) const
{
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 306b5ac..3931caa 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -53,7 +53,9 @@
#include <vector>
#include "base/printable.hh"
+#include "base/trace.hh"
#include "base/types.hh"
+#include "debug/MSHRTargets.hh"
#include "mem/cache/queue_entry.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
@@ -460,6 +462,8 @@
*/
void popTarget()
{
+ DPRINTF(MSHRTargets, "Force deallocate MSHR target: %s\n",
+ targets.front().pkt->print());
targets.pop_front();
}
@@ -502,6 +506,10 @@
void print(std::ostream &os,
int verbosity = 0,
const std::string &prefix = "") const override;
+
+ std::string cacheName;
+ std::string name() const;
+
/**
* A no-args wrapper of print(std::ostream...) meant to be
* invoked from DPRINTFs avoiding string overheads in fast mode
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 016c3f4..81a6cda 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -46,13 +46,22 @@
#include <cassert>
+#include "debug/MSHREntries.hh"
+#include "debug/MSHRTargets.hh"
#include "mem/cache/mshr.hh"
+
MSHRQueue::MSHRQueue(const std::string &_label,
- int num_entries, int reserve, int demand_reserve)
+ int num_entries, int reserve,
+ int demand_reserve, std::string cache_name = "")
: Queue<MSHR>(_label, num_entries, reserve),
- demandReserve(demand_reserve)
-{}
+ demandReserve(demand_reserve),
+ cacheName(cache_name + ".mshrQueue")
+{
+
+ for (MSHR &mshr: entries)
+ mshr.cacheName = cache_name + ".mshr";
+}
MSHR *
MSHRQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
@@ -63,15 +72,31 @@
assert(mshr->getNumTargets() == 0);
freeList.pop_front();
+ DPRINTF(MSHREntries, "Allocate MSHR %lu/%lu\n",
+ allocatedList.size() + 1, numEntries);
+
mshr->allocate(blk_addr, blk_size, pkt, when_ready, order,
alloc_on_fill);
mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
mshr->readyIter = addToReadyList(mshr);
allocated += 1;
+
return mshr;
}
void
+MSHRQueue::deallocate(MSHR* mshr)
+{
+
+ DPRINTF(MSHRTargets, "Deallocated all targets %s", mshr->print());
+ Queue<MSHR>::deallocate(mshr);
+
+ DPRINTF(MSHREntries, "Deallocate MSHR %lu/%lu\n",
+ allocatedList.size(), numEntries);
+}
+
+
+void
MSHRQueue::moveToFront(MSHR *mshr)
{
if (!mshr->inService) {
@@ -123,8 +148,16 @@
// Delete mshr if no remaining targets
if (!mshr->hasTargets() && !mshr->promoteDeferredTargets()) {
deallocate(mshr);
+ DPRINTF(MSHREntries, "Deallocate MSHR %lu/%lu\n",
+ allocatedList.size(), numEntries);
}
// Notify if MSHR queue no longer full
return was_full && !isFull();
}
+
+std::string
+MSHRQueue::name() const
+{
+ return cacheName;
+}
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index 7a34db1..4fd6bdb 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -76,7 +76,7 @@
* demand accesses.
*/
MSHRQueue(const std::string &_label, int num_entries, int reserve,
- int demand_reserve);
+ int demand_reserve, std::string cache_name);
/**
* Allocates a new MSHR for the request and size. This places the
request
@@ -96,6 +96,8 @@
MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
Tick when_ready, Counter order, bool alloc_on_fill);
+ void deallocate(MSHR* mshr);
+
/**
* Moves the MSHR to the front of the pending list if it is not
* in service.
@@ -153,6 +155,10 @@
// keep regressions unchanged
return (allocated < numEntries - (numReserve + 1 + demandReserve));
}
+
+ std::string cacheName;
+ std::string name() const;
+
};
#endif //__MEM_CACHE_MSHR_QUEUE_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9943b9ea57e351060824521f9e25192ab25403a
Gerrit-Change-Number: 46979
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet <[email protected]>
Gerrit-MessageType: newchange
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