Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47302 )
Change subject: ext: Adopt the gem5 namespace in ext/
......................................................................
ext: Adopt the gem5 namespace in ext/
Change-Id: I3da8adffdcfe9e47e88cd85b7b66f6f8e1a1757a
Signed-off-by: Daniel R. Carvalho <[email protected]>
---
M ext/sst/ExtMaster.cc
M ext/sst/ExtMaster.hh
M ext/sst/ExtSlave.cc
M ext/sst/ExtSlave.hh
M ext/sst/gem5.cc
M ext/sst/gem5.hh
6 files changed, 92 insertions(+), 71 deletions(-)
diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 3afd6b4..e727537 100644
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -56,10 +56,10 @@
using namespace SST::gem5;
using namespace SST::MemHierarchy;
-ExtMaster::ExtMaster(gem5Component *g, Output &o, ::ExternalMaster& p,
+ExtMaster::ExtMaster(gem5Component *g, Output &o, ::gem5::ExternalMaster&
p,
std::string &n) :
- Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
- gem5(g), name(n)
+ ::gem5::ExternalMaster::Port(n, p), out(o), port(p),
+ simPhase(CONSTRUCTION), gem5(g), name(n)
{
Params _p; // will be ignored
nic =
dynamic_cast<MemNIC*>(gem5->loadModuleWithComponent("memHierarchy.memNIC",
g, _p));
@@ -130,12 +130,12 @@
}
Command cmdI = ev->getCmd(); // command in - SST
- MemCmd::Command cmdO; // command out - gem5
+ ::gem5::MemCmd::Command cmdO; // command out - gem5
bool data = false;
switch (cmdI) {
- case GetS: cmdO = MemCmd::ReadReq; break;
- case GetX: cmdO = MemCmd::WriteReq; data = true; break;
+ case GetS: cmdO = ::gem5::MemCmd::ReadReq;
break;
+ case GetX: cmdO = ::gem5::MemCmd::WriteReq; data = true;
break;
case GetSEx:
case PutS:
case PutM:
@@ -158,23 +158,24 @@
CommandString[cmdI]);
}
- Request::FlagsType flags = 0;
+ ::gem5::Request::FlagsType flags = 0;
if (ev->queryFlag(MemEvent::F_LOCKED))
- flags |= Request::LOCKED_RMW;
+ flags |= ::gem5::Request::LOCKED_RMW;
if (ev->queryFlag(MemEvent::F_NONCACHEABLE))
- flags |= Request::UNCACHEABLE;
+ flags |= ::gem5::Request::UNCACHEABLE;
if (ev->isLoadLink()) {
assert(cmdI == GetS);
- cmdO = MemCmd::LoadLockedReq;
+ cmdO = ::gem5::MemCmd::LoadLockedReq;
} else if (ev->isStoreConditional()) {
assert(cmdI == GetX);
- cmdO = MemCmd::StoreCondReq;
+ cmdO = ::gem5::MemCmd::StoreCondReq;
}
- auto req = std::make_shared<Request>(ev->getAddr(), ev->getSize(),
flags, 0);
+ auto req = std::make_shared<::gem5::Request>(
+ ev->getAddr(), ev->getSize(), flags, 0);
req->setContext(ev->getGroupId());
- auto pkt = new Packet(req, cmdO);
+ auto pkt = new ::gem5::Packet(req, cmdO);
pkt->allocate();
if (data) {
pkt->setData(ev->getPayload().data());
@@ -186,7 +187,7 @@
}
bool
-ExtMaster::recvTimingResp(PacketPtr pkt) {
+ExtMaster::recvTimingResp(::gem5::PacketPtr pkt) {
if (simPhase == INIT) {
out.fatal(CALL_INFO, 1, "not prepared to handle INIT-phase
traffic\n");
}
diff --git a/ext/sst/ExtMaster.hh b/ext/sst/ExtMaster.hh
index 04e98e5..8b4020b 100644
--- a/ext/sst/ExtMaster.hh
+++ b/ext/sst/ExtMaster.hh
@@ -51,10 +51,11 @@
#include <core/component.h>
#include <elements/memHierarchy/memEvent.h>
-#include <sim/sim_object.hh>
+#include <base/addr_range.hh>
+#include <mem/external_master.hh>
#include <mem/packet.hh>
#include <mem/request.hh>
-#include <mem/external_master.hh>
+#include <sim/sim_object.hh>
namespace SST {
@@ -70,34 +71,35 @@
class gem5Component;
-class ExtMaster : public ExternalMaster::Port {
+class ExtMaster : public ::gem5::ExternalMaster::Port
+{
enum Phase { CONSTRUCTION, INIT, RUN };
Output& out;
- const ExternalMaster& port;
+ const ::gem5::ExternalMaster& port;
Phase simPhase;
gem5Component *const gem5;
const std::string name;
- std::list<PacketPtr> sendQ;
+ std::list<::gem5::PacketPtr> sendQ;
bool blocked() { return !sendQ.empty(); }
MemHierarchy::MemNIC * nic;
- struct SenderState : public Packet::SenderState
+ struct SenderState : public ::gem5::Packet::SenderState
{
MemEvent *event;
SenderState(MemEvent* e) : event(e) {}
};
- std::set<AddrRange> ranges;
+ std::set<::gem5::AddrRange> ranges;
public:
- bool recvTimingResp(PacketPtr);
+ bool recvTimingResp(::gem5::PacketPtr);
void recvReqRetry();
- ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
+ ExtMaster(gem5Component*, Output&, ::gem5::ExternalMaster&,
std::string&);
void init(unsigned phase);
void setup();
void finish();
diff --git a/ext/sst/ExtSlave.cc b/ext/sst/ExtSlave.cc
index 0e2f8b4..b9a5e78 100644
--- a/ext/sst/ExtSlave.cc
+++ b/ext/sst/ExtSlave.cc
@@ -48,13 +48,15 @@
#undef fatal
#endif
+#include <base/types.hh>
+
using namespace SST;
using namespace SST::gem5;
using namespace SST::MemHierarchy;
ExtSlave::ExtSlave(gem5Component *g5c, Output &out,
- ::ExternalSlave& port, std::string &name) :
- Port(name, port),
+ ::gem5::ExternalSlave& port, std::string &name) :
+ ::gem5::ExternalSlave::Port(name, port),
comp(g5c), out(out), simPhase(CONSTRUCTION), initPackets(NULL),
link(comp->configureLink(name, new Event::Handler<ExtSlave>(this,
&ExtSlave::handleEvent)))
@@ -64,7 +66,8 @@
}
}
-void ExtSlave::init(unsigned phase)
+void
+ExtSlave::init(unsigned phase)
{
simPhase = INIT;
if (initPackets) {
@@ -78,15 +81,16 @@
}
void
-ExtSlave::recvFunctional(PacketPtr pkt)
+ExtSlave::recvFunctional(::gem5::PacketPtr pkt)
{
if (simPhase == CONSTRUCTION) {
if (initPackets == NULL) {
initPackets = new std::list<MemEvent*>;
}
- ::MemCmd::Command pktCmd = (::MemCmd::Command)pkt->cmd.toInt();
- assert(pktCmd == ::MemCmd::WriteReq);
- Addr a = pkt->getAddr();
+ ::gem5::MemCmd::Command pktCmd =
+ (::gem5::MemCmd::Command)pkt->cmd.toInt();
+ assert(pktCmd == ::gem5::MemCmd::WriteReq);
+ ::gem5::Addr a = pkt->getAddr();
MemEvent* ev = new MemEvent(comp, a, a, GetX);
ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
initPackets->push_back(ev);
@@ -96,17 +100,17 @@
}
bool
-ExtSlave::recvTimingReq(PacketPtr pkt)
+ExtSlave::recvTimingReq(::gem5::PacketPtr pkt)
{
Command cmd;
- switch ((::MemCmd::Command)pkt->cmd.toInt()) {
- case ::MemCmd::HardPFReq:
- case ::MemCmd::SoftPFReq:
- case ::MemCmd::LoadLockedReq:
- case ::MemCmd::ReadExReq:
- case ::MemCmd::ReadReq: cmd = GetS; break;
- case ::MemCmd::StoreCondReq:
- case ::MemCmd::WriteReq: cmd = GetX; break;
+ switch ((::gem5::MemCmd::Command)pkt->cmd.toInt()) {
+ case ::gem5::MemCmd::HardPFReq:
+ case ::gem5::MemCmd::SoftPFReq:
+ case ::gem5::MemCmd::LoadLockedReq:
+ case ::gem5::MemCmd::ReadExReq:
+ case ::gem5::MemCmd::ReadReq: cmd = GetS; break;
+ case ::gem5::MemCmd::StoreCondReq:
+ case ::gem5::MemCmd::WriteReq: cmd = GetX; break;
default:
out.fatal(CALL_INFO, 1, "Don't know how to convert gem5 packet "
"command %s to SST\n", pkt->cmd.toString().c_str());
@@ -114,10 +118,13 @@
auto ev = new MemEvent(comp, pkt->getAddr(), pkt->getAddr(), cmd);
ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
- if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::LoadLockedReq)
+ if ((::gem5::MemCmd::Command)pkt->cmd.toInt() ==
+ ::gem5::MemCmd::LoadLockedReq) {
ev->setLoadLink();
- else if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::StoreCondReq)
+ } else if ((::gem5::MemCmd::Command)pkt->cmd.toInt() ==
+ ::gem5::MemCmd::StoreCondReq) {
ev->setStoreConditional();
+ }
if (pkt->req->isLockedRMW()) ev->setFlag(MemEvent::F_LOCKED);
if (pkt->req->isUncacheable()) ev->setFlag(MemEvent::F_NONCACHEABLE);
@@ -152,7 +159,7 @@
PacketMap_t::iterator mi = PacketMap.find(id);
if (mi != PacketMap.end()) { // replying to prior request
- PacketPtr pkt = mi->second;
+ ::gem5::PacketPtr pkt = mi->second;
PacketMap.erase(mi);
pkt->makeResponse(); // Convert to a response packet
@@ -175,10 +182,10 @@
// make Req/Pkt for Snoop/no response needed
// presently no consideration for masterId, packet type, flags...
- RequestPtr req = std::make_shared<Request>(
+ ::gem5::RequestPtr req = std::make_shared<::gem5::Request>(
event->getAddr(), event->getSize(), 0, 0);
- auto pkt = new Packet(req, ::MemCmd::InvalidateReq);
+ auto pkt = new ::gem5::Packet(req, ::gem5::MemCmd::InvalidateReq);
// Clear out bus delay notifications
pkt->headerDelay = pkt->payloadDelay = 0;
diff --git a/ext/sst/ExtSlave.hh b/ext/sst/ExtSlave.hh
index cef7c1e..fa32655 100644
--- a/ext/sst/ExtSlave.hh
+++ b/ext/sst/ExtSlave.hh
@@ -45,12 +45,16 @@
#ifndef EXT_SST_EXTSLAVE_HH
#define EXT_SST_EXTSLAVE_HH
+#include <list>
+#include <string>
+
#include <core/interfaces/simpleMem.h>
-#include <sim/sim_object.hh>
+#include <base/logging.hh>
#include <mem/packet.hh>
#include <mem/request.hh>
#include <mem/external_slave.hh>
+#include <sim/sim_object.hh>
namespace SST {
class Link;
@@ -60,25 +64,26 @@
class gem5Component;
-class ExtSlave : public ExternalSlave::Port {
+class ExtSlave : public ::gem5::ExternalSlave::Port
+{
public:
const std::string name;
bool
- recvTimingSnoopResp(PacketPtr packet)
+ recvTimingSnoopResp(::gem5::PacketPtr packet)
{
fatal("recvTimingSnoopResp unimplemented");
return false;
}
- bool recvTimingReq(PacketPtr packet);
+ bool recvTimingReq(::gem5::PacketPtr packet);
- void recvFunctional(PacketPtr packet);
+ void recvFunctional(::gem5::PacketPtr packet);
void recvRespRetry();
- Tick
- recvAtomic(PacketPtr packet)
+ ::gem5::Tick
+ recvAtomic(::gem5::PacketPtr packet)
{
fatal("recvAtomic unimplemented");
}
@@ -91,14 +96,14 @@
std::list<MemEvent*>* initPackets;
Link* link;
- std::list<PacketPtr> respQ;
+ std::list<::gem5::PacketPtr> respQ;
bool blocked() { return !respQ.empty(); }
- typedef std::map<Event::id_type, ::Packet*> PacketMap_t;
+ typedef std::map<Event::id_type, ::gem5::Packet*> PacketMap_t;
PacketMap_t PacketMap; // SST Event id -> gem5 Packet*
public:
- ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&);
+ ExtSlave(gem5Component*, Output&, ::gem5::ExternalSlave&,
std::string&);
void init(unsigned phase);
void
diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index 3d48e93..efe73eb 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -108,14 +108,15 @@
splitCommandArgs(gem5DbgFlags, flags);
for (auto flag : flags) {
dbg.output(CALL_INFO, " Setting Debug Flag [%s]\n", flag);
- setDebugFlag(flag);
+ ::gem5::setDebugFlag(flag);
}
- ExternalMaster::registerHandler("sst", this); // these are idempotent
- ExternalSlave ::registerHandler("sst", this);
+ // These are idempotent
+ ::gem5::ExternalMaster::registerHandler("sst", this);
+ ::gem5::ExternalSlave::registerHandler("sst", this);
- // Initialize m5 special signal handling.
- initSignals();
+ // Initialize gem5's special signal handling.
+ ::gem5::initSignals();
initPython(args.size(), &args[0]);
@@ -172,11 +173,12 @@
m->clock();
}
- GlobalSimLoopExitEvent *event = simulate(sim_cycles);
+ ::gem5::GlobalSimLoopExitEvent *event = ::gem5::simulate(sim_cycles);
++clocks_processed;
if (event != simulate_limit_event) {
info.output("exiting: curTick()=%lu cause=`%s` code=%d\n",
- curTick(), event->getCause().c_str(), event->getCode());
+ ::gem5::curTick(), event->getCause().c_str(),
+ event->getCode());
primaryComponentOKToEndSim();
return true;
}
@@ -248,9 +250,9 @@
}
}
-ExternalMaster::Port*
+::gem5::ExternalMaster::Port*
gem5Component::getExternalPort(const std::string &name,
- ExternalMaster &owner, const std::string &port_data)
+ ::gem5::ExternalMaster &owner, const std::string &port_data)
{
std::string s(name); // bridges non-& result and &-arg
auto master = new ExtMaster(this, info, owner, s);
@@ -258,9 +260,9 @@
return master;
}
-ExternalSlave::Port*
+::gem5::ExternalSlave::Port*
gem5Component::getExternalPort(const std::string &name,
- ExternalSlave &owner, const std::string &port_data)
+ ::gem5::ExternalSlave &owner, const std::string &port_data)
{
std::string s(name); // bridges non-& result and &-arg
auto slave = new ExtSlave(this, info, owner, s);
diff --git a/ext/sst/gem5.hh b/ext/sst/gem5.hh
index 0f1bed8..4dc0213 100644
--- a/ext/sst/gem5.hh
+++ b/ext/sst/gem5.hh
@@ -45,12 +45,15 @@
#ifndef EXT_SST_GEM5_HH
#define EXT_SST_GEM5_HH
+#include <cstdint>
#include <string>
#include <vector>
#include <core/sst_config.h>
#include <core/component.h>
+#include <mem/external_master.hh>
+#include <mem/external_slave.hh>
#include <sim/simulate.hh>
#include "ExtMaster.hh"
@@ -60,8 +63,9 @@
namespace gem5 {
class gem5Component : public SST::Component,
- public ExternalSlave::Handler,
- public ExternalMaster::Handler {
+ public ::gem5::ExternalSlave::Handler,
+ public ::gem5::ExternalMaster::Handler
+{
private:
Output dbg;
@@ -83,12 +87,12 @@
virtual void finish();
bool clockTick(Cycle_t);
- virtual ExternalMaster::Port *getExternalPort(
- const std::string &name, ExternalMaster &owner,
+ virtual ::gem5::ExternalMaster::Port *getExternalPort(
+ const std::string &name, ::gem5::ExternalMaster &owner,
const std::string &port_data);
- virtual ExternalSlave::Port *getExternalPort(
- const std::string &name, ExternalSlave &owner,
+ virtual ::gem5::ExternalSlave::Port *getExternalPort(
+ const std::string &name, ::gem5::ExternalSlave &owner,
const std::string &port_data);
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47302
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3da8adffdcfe9e47e88cd85b7b66f6f8e1a1757a
Gerrit-Change-Number: 47302
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
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