Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40902 )
Change subject: arch-power: Add PC-relative arithmetic instructions
......................................................................
arch-power: Add PC-relative arithmetic instructions
This adds the following instructions.
* Add PC Immediate Shifted (addpcis)
Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40902
Reviewed-by: Boris Shingarov <shinga...@labware.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
4 files changed, 81 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 2035b5c..25c8691 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -219,6 +219,51 @@
std::string
+IntDispArithOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool printSrcs = true;
+ bool printDisp = true;
+ bool negateDisp = false;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (myMnemonic == "addpcis") {
+ printSrcs = false;
+ if (d == 0) {
+ myMnemonic = "lnia";
+ printDisp = false;
+ } else if (d < 0) {
+ myMnemonic = "subpcis";
+ negateDisp = true;
+ }
+ }
+
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+ // Print the first destination only
+ if (_numDestRegs > 0)
+ printReg(ss, destRegIdx(0));
+
+ // Print the source register
+ if (_numSrcRegs > 0 && printSrcs) {
+ if (_numDestRegs > 0)
+ ss << ", ";
+ printReg(ss, srcRegIdx(0));
+ }
+
+ // Print the displacement
+ if (printDisp)
+ ss << ", " << (negateDisp ? -d : d);
+
+ return ss.str();
+}
+
+
+std::string
IntShiftOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
{
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index daef626..aafbbec 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -161,6 +161,27 @@
/**
+ * Class for integer arithmetic operations with displacement.
+ */
+class IntDispArithOp : public IntArithOp
+{
+ protected:
+
+ int64_t d;
+
+ /// Constructor
+ IntDispArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntArithOp(mnem, _machInst, __opClass),
+ d(sext<16>((machInst.d0 << 6) | (machInst.d1 << 1) | machInst.d2))
+ {
+ }
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index cc3b9f4..beacd6f 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -163,6 +163,10 @@
528: bcctr({{ NIA = CTR & -4ULL; }});
560: bctar({{ NIA = TAR & -4ULL; }}, true);
}
+
+ default: decode DX_XO {
+ 2: IntDispArithOp::addpcis({{ Rt = NIA + (d << 16); }});
+ }
}
format IntRotateOp {
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 8583ba0..183c08b 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -168,6 +168,17 @@
}};
+// Integer instructions with displacement that perform arithmetic.
+// There are no control flags to set.
+def format IntDispArithOp(code, inst_flags = []) {{
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntDispArithOp', code, inst_flags,
BasicDecode,
+ BasicConstructor)
+}};
+
+
// Integer instructions that perform logic operations. The result is
// always written into Ra. All instructions have 2 versions depending on
// whether the Rc bit is set to compute the CR0 code. This is determined
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Gerrit-Change-Number: 40902
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-Reviewer: Boris Shingarov <shinga...@labware.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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