Tom Rollet has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47040 )
Change subject: mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from
Named
......................................................................
mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named
With this change, when using a DPRINTF statment on a class inheriting
from the Queue or QueueEntry class, the name at the start of the log
line will be meaningful.
Currently affected classes:
MSHRqueue
MSHR
MSHR::TargetList
WriteQueue
WriteQueueEntry
Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47040
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
Maintainer: Daniel Carvalho <oda...@yahoo.com.br>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/mem/cache/base.cc
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.hh
10 files changed, 41 insertions(+), 26 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 928c30b..48731cf 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -76,8 +76,8 @@
: ClockedObject(p),
cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
- mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve), // see below
- writeBuffer("write buffer", p.write_buffers, p.mshrs), // see below
+ mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve, p.name),
+ writeBuffer("write buffer", p.write_buffers, p.mshrs, p.name),
tags(p.tags),
compressor(p.compressor),
prefetcher(p.prefetcher),
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index bb4e8df..2927d05 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -57,16 +57,21 @@
#include "mem/request.hh"
#include "sim/core.hh"
-MSHR::MSHR() : downstreamPending(false),
- pendingModified(false),
- postInvalidate(false), postDowngrade(false),
- wasWholeLineWrite(false), isForward(false)
+MSHR::MSHR(const std::string &name)
+ : QueueEntry(name),
+ downstreamPending(false),
+ pendingModified(false),
+ postInvalidate(false), postDowngrade(false),
+ wasWholeLineWrite(false), isForward(false),
+ targets(name + ".targets"),
+ deferredTargets(name + ".deferredTargets")
{
}
-MSHR::TargetList::TargetList()
- : needsWritable(false), hasUpgrade(false), allocOnFill(false),
- hasFromCache(false)
+MSHR::TargetList::TargetList(const std::string &name)
+ : Named(name),
+ needsWritable(false), hasUpgrade(false),
+ allocOnFill(false), hasFromCache(false)
{}
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 306b5ac..b23ed28 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -161,7 +161,7 @@
{}
};
- class TargetList : public std::list<Target>
+ class TargetList : public std::list<Target>, public Named
{
public:
@@ -175,7 +175,7 @@
*/
bool hasFromCache;
- TargetList();
+ TargetList(const std::string &name = ".unnamedTargetList");
/**
* Use the provided packet and the source to update the
@@ -416,7 +416,7 @@
bool handleSnoop(PacketPtr target, Counter order);
/** A simple constructor. */
- MSHR();
+ MSHR(const std::string &name);
/**
* Returns the current number of allocated targets.
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 016c3f4..cea32fd 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -49,8 +49,9 @@
#include "mem/cache/mshr.hh"
MSHRQueue::MSHRQueue(const std::string &_label,
- int num_entries, int reserve, int demand_reserve)
- : Queue<MSHR>(_label, num_entries, reserve),
+ int num_entries, int reserve,
+ int demand_reserve, std::string cache_name = "")
+ : Queue<MSHR>(_label, num_entries, reserve, cache_name
+ ".mshr_queue"),
demandReserve(demand_reserve)
{}
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index 7a34db1..98147fa 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -76,7 +76,7 @@
* demand accesses.
*/
MSHRQueue(const std::string &_label, int num_entries, int reserve,
- int demand_reserve);
+ int demand_reserve, std::string cache_name);
/**
* Allocates a new MSHR for the request and size. This places the
request
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index 8ab0cbb..81999a7 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -50,6 +50,7 @@
#include <type_traits>
#include "base/logging.hh"
+#include "base/named.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Drain.hh"
@@ -63,7 +64,7 @@
* the write buffer.
*/
template<class Entry>
-class Queue : public Drainable
+class Queue : public Drainable, public Named
{
static_assert(std::is_base_of<QueueEntry, Entry>::value,
"Entry must be derived from QueueEntry");
@@ -126,10 +127,12 @@
* @param num_entries The number of entries in this queue.
* @param reserve The extra overflow entries needed.
*/
- Queue(const std::string &_label, int num_entries, int reserve) :
+ Queue(const std::string &_label, int num_entries, int reserve,
+ const std::string &name) :
+ Named(name),
label(_label), numEntries(num_entries + reserve),
- numReserve(reserve), entries(numEntries), _numInService(0),
- allocated(0)
+ numReserve(reserve), entries(numEntries, name + ".entry"),
+ _numInService(0), allocated(0)
{
for (int i = 0; i < numEntries; ++i) {
freeList.push_back(&entries[i]);
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 48d17c7..9e528da 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -46,6 +46,7 @@
#ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
#define __MEM_CACHE_QUEUE_ENTRY_HH__
+#include "base/named.hh"
#include "base/types.hh"
#include "mem/packet.hh"
@@ -55,7 +56,7 @@
* A queue entry base class, to be used by both the MSHRs and
* write-queue entries.
*/
-class QueueEntry : public Packet::SenderState
+class QueueEntry : public Packet::SenderState, public Named
{
/**
@@ -117,8 +118,9 @@
/** True if the entry targets the secure memory space. */
bool isSecure;
- QueueEntry()
- : readyTime(0), _isUncacheable(false),
+ QueueEntry(const std::string &name)
+ : Named(name),
+ readyTime(0), _isUncacheable(false),
inService(false), order(0), blkAddr(0), blkSize(0),
isSecure(false)
{}
diff --git a/src/mem/cache/write_queue.cc b/src/mem/cache/write_queue.cc
index 2e3cc93..fd55257 100644
--- a/src/mem/cache/write_queue.cc
+++ b/src/mem/cache/write_queue.cc
@@ -49,8 +49,9 @@
#include "mem/cache/write_queue_entry.hh"
WriteQueue::WriteQueue(const std::string &_label,
- int num_entries, int reserve)
- : Queue<WriteQueueEntry>(_label, num_entries, reserve)
+ int num_entries, int reserve, const std::string
&name)
+ : Queue<WriteQueueEntry>(_label, num_entries, reserve,
+ name + ".write_queue")
{}
WriteQueueEntry *
diff --git a/src/mem/cache/write_queue.hh b/src/mem/cache/write_queue.hh
index a072468..2705232 100644
--- a/src/mem/cache/write_queue.hh
+++ b/src/mem/cache/write_queue.hh
@@ -65,7 +65,8 @@
* @param reserve The maximum number of entries needed to satisfy
* any access.
*/
- WriteQueue(const std::string &_label, int num_entries, int reserve);
+ WriteQueue(const std::string &_label, int num_entries, int reserve,
+ const std::string &name);
/**
* Allocates a new WriteQueueEntry for the request and size. This
diff --git a/src/mem/cache/write_queue_entry.hh
b/src/mem/cache/write_queue_entry.hh
index d50de35..cfb4a11 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -112,7 +112,9 @@
public:
/** A simple constructor. */
- WriteQueueEntry() {}
+ WriteQueueEntry(const std::string &name)
+ : QueueEntry(name)
+ {}
/**
* Allocate a miss to this entry.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Gerrit-Change-Number: 47040
Gerrit-PatchSet: 3
Gerrit-Owner: Tom Rollet <tom.rol...@huawei.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: Tom Rollet <tom.rol...@huawei.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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