Sandipan Das has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40906 )

Change subject: arch-power: Add word divide-extended instructions
......................................................................

arch-power: Add word divide-extended instructions

This adds the following instructions.
  * Divide Word Extended (divwe[o][.])
  * Divide Word Extended Unsigned (divweu[o][.])

Change-Id: Ie399269938c8e120ece667ce3fc9c6fe1d74faca
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40906
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/isa/decoder.isa
1 file changed, 36 insertions(+), 0 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e8fcb66..258a696 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -574,6 +574,42 @@
             266: IntSumOp::add({{ Ra }}, {{ Rb }});

             format IntArithCheckRcOp {
+                395: divweu({{
+                    uint32_t src1 = Ra_ud;
+                    uint32_t src2 = Rb_ud;
+                    uint64_t res;
+                    if (src2 != 0) {
+                        res = ((uint64_t)src1 << 32) / src2;
+                        if (res <= UINT32_MAX) {
+                            Rt = (uint32_t)res;
+                        } else {
+                            Rt = 0;
+                            setOV = true;
+                        }
+                    } else {
+                        Rt = 0;
+                        setOV = true;
+                    }
+                }}, true);
+
+                427: divwe({{
+                    int32_t src1 = Ra_sw;
+                    int32_t src2 = Rb_sw;
+                    int64_t res;
+                    if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+                        res = ((int64_t)src1 << 32) / src2;
+                        if (res == (int32_t)res) {
+                            Rt = (uint32_t)res;
+                        } else {
+                            Rt = 0;
+                            setOV = true;
+                        }
+                    } else {
+                        Rt = 0;
+                        setOV = true;
+                    }
+                }}, true);
+
                 459: divwu({{
                     uint32_t src1 = Ra_uw;
                     uint32_t src2 = Rb_uw;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie399269938c8e120ece667ce3fc9c6fe1d74faca
Gerrit-Change-Number: 40906
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Sandipan Das <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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