Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40913 )
Change subject: arch-power: Fix compare instructions
......................................................................
arch-power: Fix compare instructions
Now that 64-bit registers are being used, instead of always
performing a 32-bit comparison, these instructions must use
the L field to determine the type of comparison to be made.
The comparison can either be 32-bit or 64-bit. This fixes
the following instructions.
* Compare (cmp)
* Compare Logical (cmpl)
* Compare Immediate (cmpi)
* Compare Logical Immediate (cmpli)
Change-Id: Ia7655ffa463214c24e094e01d4188decf6486904
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40913
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/isa/decoder.isa
1 file changed, 16 insertions(+), 4 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 221365e..89effee 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -74,11 +74,17 @@
}
10: IntImmCompLogicOp::cmpli({{
- cr = makeCRFieldUnsigned(Ra_uw, ui, xer.so);
+ if (l)
+ cr = makeCRFieldUnsigned(Ra, ui, xer.so);
+ else
+ cr = makeCRFieldUnsigned((uint32_t) Ra, ui, xer.so);
}});
11: IntImmCompOp::cmpi({{
- cr = makeCRFieldSigned(Ra_sw, si, xer.so);
+ if (l)
+ cr = makeCRFieldSigned(Ra, si, xer.so);
+ else
+ cr = makeCRFieldSigned((int32_t) Ra, si, xer.so);
}});
format IntImmArithOp {
@@ -218,7 +224,10 @@
31: decode X_XO {
0: IntCompOp::cmp({{
- cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
+ if (l)
+ cr = makeCRFieldSigned(Ra, Rb, xer.so);
+ else
+ cr = makeCRFieldSigned((int32_t)Ra, (int32_t)Rb, xer.so);
}});
format LoadIndexOp {
@@ -245,7 +254,10 @@
}
32: IntCompOp::cmpl({{
- cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
+ if (l)
+ cr = makeCRFieldUnsigned(Ra, Rb, xer.so);
+ else
+ cr = makeCRFieldUnsigned((uint32_t)Ra, (uint32_t)Rb,
xer.so);
}});
52: LoadIndexOp::lbarx({{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia7655ffa463214c24e094e01d4188decf6486904
Gerrit-Change-Number: 40913
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Sandipan Das <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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