Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40914 )
Change subject: arch-power: Fix disassembly for compare instructions
......................................................................
arch-power: Fix disassembly for compare instructions
This fixes disassembly generated for integer compare
instructions based on the type of operands, the type of
comparison to be made and the special use cases for which
the Power ISA provides extended mnemonics.
Change-Id: Ia052bef9589cc3ed290400390028398be28c8eff
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40914
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
2 files changed, 161 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 61b7f08..95de652 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -49,8 +49,7 @@
myMnemonic == "mtxer" ||
myMnemonic == "mtlr" ||
myMnemonic == "mtctr" ||
- myMnemonic == "mttar" ||
- myMnemonic == "cmpi") {
+ myMnemonic == "mttar") {
printDest = false;
} else if (myMnemonic == "mfcr" ||
myMnemonic == "mfxer" ||
@@ -275,6 +274,157 @@
std::string
+IntCompOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool printFieldPrefix = false;
+ bool printLength = true;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (myMnemonic == "cmp" ||
+ myMnemonic == "cmpl") {
+ myMnemonic += l ? "d" : "w";
+ printFieldPrefix = true;
+ printLength = false;
+ }
+
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+ // Print the first destination only
+ if (printFieldPrefix) {
+ if (bf > 0)
+ ss << "cr" << (int) bf;
+ } else {
+ ss << (int) bf;
+ }
+
+ // Print the length
+ if (printLength) {
+ if (!printFieldPrefix || bf > 0)
+ ss << ", ";
+ ss << (int) l;
+ }
+
+ // Print the first source register
+ if (_numSrcRegs > 0) {
+ if (!printFieldPrefix || bf > 0 || printLength)
+ ss << ", ";
+ printReg(ss, srcRegIdx(0));
+
+ // Print the second source register
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
+ }
+
+ return ss.str();
+}
+
+
+std::string
+IntImmCompOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool printFieldPrefix = false;
+ bool printLength = true;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (myMnemonic == "cmpi") {
+ myMnemonic = l ? "cmpdi" : "cmpwi";
+ printFieldPrefix = true;
+ printLength = false;
+ }
+
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+ // Print the first destination only
+ if (printFieldPrefix) {
+ if (bf > 0)
+ ss << "cr" << (int) bf;
+ } else {
+ ss << (int) bf;
+ }
+
+ // Print the length
+ if (printLength) {
+ if (!printFieldPrefix || bf > 0)
+ ss << ", ";
+ ss << (int) l;
+ }
+
+ // Print the first source register
+ if (_numSrcRegs > 0) {
+ if (!printFieldPrefix || bf > 0 || printLength)
+ ss << ", ";
+ printReg(ss, srcRegIdx(0));
+ }
+
+ // Print the immediate value
+ ss << ", " << si;
+
+ return ss.str();
+}
+
+
+std::string
+IntImmCompLogicOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool printFieldPrefix = false;
+ bool printLength = true;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (myMnemonic == "cmpli") {
+ myMnemonic = l ? "cmpldi" : "cmplwi";
+ printFieldPrefix = true;
+ printLength = false;
+ }
+
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+ // Print the first destination only
+ if (printFieldPrefix) {
+ if (bf > 0)
+ ss << "cr" << (int) bf;
+ } else {
+ ss << (int) bf;
+ }
+
+ // Print the length
+ if (printLength) {
+ if (!printFieldPrefix || bf > 0)
+ ss << ", ";
+ ss << (int) l;
+ }
+
+ // Print the first source register
+ if (_numSrcRegs > 0) {
+ if (!printFieldPrefix || bf > 0 || printLength)
+ ss << ", ";
+ printReg(ss, srcRegIdx(0));
+ }
+
+ // Print the immediate value
+ ss << ", " << ui;
+
+ return ss.str();
+}
+
+
+std::string
IntShiftOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
{
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 6fb797a..64ba635 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -423,6 +423,9 @@
bf(machInst.bf)
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
@@ -441,6 +444,9 @@
si(sext<16>(machInst.si))
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
@@ -459,6 +465,9 @@
ui(machInst.ui)
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia052bef9589cc3ed290400390028398be28c8eff
Gerrit-Change-Number: 40914
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Sandipan Das <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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