Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40924 )
Change subject: arch-power: Refactor shift instructions
......................................................................
arch-power: Refactor shift instructions
This changes the format for integer shift instructions
such that the computation of the carry bit is implicitly
handled rather than including it in the definition of an
instruction.
Change-Id: Ib916597287efd51b2c9e8781209a8019f2fc38e8
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40924
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
3 files changed, 75 insertions(+), 65 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 481b11b..7a8c201 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -579,13 +579,14 @@
/**
- * Class for integer operations with a shift.
+ * Class for integer operations with a shift value obtained from
+ * a register or an instruction field.
*/
class IntShiftOp : public IntOp
{
protected:
- uint32_t sh;
+ uint8_t sh;
/// Constructor
IntShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 1ec2013..859ccf2 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -240,15 +240,15 @@
23: lwzx({{ Rt = Mem_uw; }});
}
- format IntLogicOp {
- 24: slw({{
- if (Rb & 0x20) {
- Ra = 0;
- } else {
- Ra = Rs << (Rb & 0x1f);
- }
- }});
+ 24: IntShiftOp::slw({{
+ if (Rb & 0x20) {
+ Ra = 0;
+ } else {
+ Ra = Rs << (Rb & 0x1f);
+ }
+ }});
+ format IntLogicOp {
26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
28: and({{ Ra = Rs & Rb; }}, true);
}
@@ -499,7 +499,7 @@
535: lfsx({{ Ft_sf = Mem_sf; }});
}
- 536: IntLogicOp::srw({{
+ 536: IntShiftOp::srw({{
if (Rb & 0x20) {
Ra = 0;
} else {
@@ -586,63 +586,49 @@
790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});
- 792: IntLogicOp::sraw({{
- bool shiftSetCA = false;
- int32_t s = Rs;
- if (Rb == 0) {
- Ra = Rs;
- shiftSetCA = true;
- } else if (Rb & 0x20) {
- if (s < 0) {
- Ra = (uint32_t)-1;
- if (s & 0x7fffffff) {
- shiftSetCA = true;
+ format IntShiftOp {
+ 792: sraw({{
+ int32_t s = Rs;
+ if (Rb == 0) {
+ Ra = Rs;
+ setCA = true;
+ } else if (Rb & 0x20) {
+ if (s < 0) {
+ Ra = (uint32_t)-1;
+ if (s & 0x7fffffff) {
+ setCA = true;
+ } else {
+ setCA = false;
+ }
} else {
- shiftSetCA = false;
+ Ra = 0;
+ setCA = false;
}
} else {
- Ra = 0;
- shiftSetCA = false;
+ Ra = s >> (Rb & 0x1f);
+ if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
+ setCA = true;
+ } else {
+ setCA = false;
+ }
}
- } else {
- Ra = s >> (Rb & 0x1f);
- if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
- shiftSetCA = true;
- } else {
- shiftSetCA = false;
- }
- }
- Xer xer1 = XER;
- if (shiftSetCA) {
- xer1.ca = 1;
- } else {
- xer1.ca = 0;
- }
- XER = xer1;
- }});
+ }}, true);
- 824: IntShiftOp::srawi({{
- bool shiftSetCA = false;
- if (sh == 0) {
- Ra = Rs;
- shiftSetCA = false;
- } else {
- int32_t s = Rs;
- Ra = s >> sh;
- if (s < 0 && (s << (32 - sh)) != 0) {
- shiftSetCA = true;
+ 824: srawi({{
+ if (sh == 0) {
+ Ra = Rs;
+ setCA = false;
} else {
- shiftSetCA = false;
+ int32_t s = Rs;
+ Ra = s >> sh;
+ if (s < 0 && (s << (32 - sh)) != 0) {
+ setCA = true;
+ } else {
+ setCA = false;
+ }
}
- }
- Xer xer1 = XER;
- if (shiftSetCA) {
- xer1.ca = 1;
- } else {
- xer1.ca = 0;
- }
- XER = xer1;
- }});
+ }}, true);
+ }
854: MiscOp::eieio({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
855: LoadIndexOp::lfiwax({{ Ft_uw = Mem; }});
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index b00e7fc..d8abd5a 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -72,6 +72,16 @@
}
'''
+setCACode = '''
+ if (setCA) {
+ xer.ca = 1;
+ xer.ca32 = 1;
+ } else {
+ xer.ca = 0;
+ xer.ca32 = 0;
+ }
+'''
+
setOVCode = '''
if (setOV) {
xer.ov = 1;
@@ -267,13 +277,26 @@
}};
-// Integer instructions with a shift amount. As above, except inheriting
-// from the IntShiftOp class.
-def format IntShiftOp(code, inst_flags = []) {{
+// Integer instructions that perform shift operations. All of these
+// instructions write to Ra and use Rs as a source register. The shift
+// value is obtained from an register or an instruction field. If it
+// from a register, Rb is also used as a source register. In certain
+// situations, the carry bits have to be set and this is dealt with
+// using the 'setCA' boolean in decoder.isa. We need two versions for
+// each instruction to deal with the Rc bit.
+def format IntShiftOp(code, computeCA = 0, inst_flags = []) {{
dict = {'result':'Ra'}
+ # Add code to setup variables and access XER if necessary
+ code = 'GEM5_VAR_USED bool setCA = false;\n' + code
+
# Code when Rc is set
- code_rc1 = code + readXERCode + computeCR0Code % dict
+ code_rc1 = readXERCode + code + computeCR0Code % dict
+
+ # Add code for calculating the carry, if needed
+ if computeCA:
+ code = readXERCode + code + setCACode + setXERCode
+ code_rc1 += setCACode + setXERCode
# Generate the first class
(header_output, decoder_output, decode_block, exec_output) = \
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib916597287efd51b2c9e8781209a8019f2fc38e8
Gerrit-Change-Number: 40924
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Sandipan Das <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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