Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40942 )
Change subject: arch-power: Add hardware features
......................................................................
arch-power: Add hardware features
This adds definitions for the hardware feature bits that
are currently available from the AT_HWCAP and AT_HWCAP2
auxv entries for the Power architecture. These are being
defined for future use.
Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40942
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/process.hh
1 file changed, 41 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index 9f2ce4b..ea5e957 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -55,4 +55,45 @@
} // namespace gem5
+enum PowerHWCAPFeature
+{
+ HWCAP_FEATURE_32 = 1ULL << 31, // Always set for powerpc64
+ HWCAP_FEATURE_64 = 1ULL << 30, // Always set for powerpc64
+ HWCAP_FEATURE_HAS_ALTIVEC = 1ULL << 28,
+ HWCAP_FEATURE_HAS_FPU = 1ULL << 27,
+ HWCAP_FEATURE_HAS_MMU = 1ULL << 26,
+ HWCAP_FEATURE_UNIFIED_CACHE = 1ULL << 24,
+ HWCAP_FEATURE_NO_TB = 1ULL << 20, // 601/403gx have no timebase
+ HWCAP_FEATURE_POWER4 = 1ULL << 19, // POWER4 ISA 2.00
+ HWCAP_FEATURE_POWER5 = 1ULL << 18, // POWER5 ISA 2.02
+ HWCAP_FEATURE_POWER5_PLUS = 1ULL << 17, // POWER5+ ISA 2.03
+ HWCAP_FEATURE_CELL_BE = 1ULL << 16, // CELL Broadband Engine
+ HWCAP_FEATURE_BOOKE = 1ULL << 15, // ISA Category Embedded
+ HWCAP_FEATURE_SMT = 1ULL << 14, // Simultaneous
Multi-Threading
+ HWCAP_FEATURE_ICACHE_SNOOP = 1ULL << 13,
+ HWCAP_FEATURE_ARCH_2_05 = 1ULL << 12, // ISA 2.05
+ HWCAP_FEATURE_PA6T = 1ULL << 11, // PA Semi 6T Core
+ HWCAP_FEATURE_HAS_DFP = 1ULL << 10, // Decimal FP Unit
+ HWCAP_FEATURE_POWER6_EXT = 1ULL << 9, // P6 + mffgpr/mftgpr
+ HWCAP_FEATURE_ARCH_2_06 = 1ULL << 8, // ISA 2.06
+ HWCAP_FEATURE_HAS_VSX = 1ULL << 7, // P7 Vector Extension
+ HWCAP_FEATURE_PSERIES_PERFMON_COMPAT = 1ULL << 6,
+ HWCAP_FEATURE_TRUE_LE = 1ULL << 1,
+ HWCAP_FEATURE_PPC_LE = 1ULL << 0
+};
+
+enum PowerHWCAP2Feature
+{
+ HWCAP2_FEATURE_ARCH_2_07 = 1ULL << 31, // ISA 2.07
+ HWCAP2_FEATURE_HAS_HTM = 1ULL << 30, // Hardware Transactional
Memory
+ HWCAP2_FEATURE_HAS_DSCR = 1ULL << 29, // Data Stream Control
Register
+ HWCAP2_FEATURE_HAS_EBB = 1ULL << 28, // Event Base Branching
+ HWCAP2_FEATURE_HAS_ISEL = 1ULL << 27, // Integer Select
+ HWCAP2_FEATURE_HAS_TAR = 1ULL << 26, // Target Address Register
+ HWCAP2_FEATURE_HAS_VCRYPTO = 1ULL << 25, // Vector AES category
+ HWCAP2_FEATURE_HTM_NOSC = 1ULL << 24,
+ HWCAP2_FEATURE_ARCH_3_00 = 1ULL << 23, // ISA 3.0
+ HWCAP2_FEATURE_HAS_IEEE128 = 1ULL << 22, // VSX IEEE Binary Float
128-bit
+};
+
#endif // __POWER_PROCESS_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Gerrit-Change-Number: 40942
Gerrit-PatchSet: 12
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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