Melissa Jost has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47839 )
Change subject: learning-gem5: This commit changes variable names in the
tutorial
......................................................................
learning-gem5: This commit changes variable names in the tutorial
Changed files from part 1 and part 2 of the learning-gem5
tutorial to use variable names int_requestor,int_responder,
cpu_side_ports, and mem_side_ports instead of master and slave.
Change-Id: I06ba4a337d947d22c39b5de3ba6700d64bda02c4
---
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/configs/learning_gem5/part1/caches.py
b/configs/learning_gem5/part1/caches.py
index c9df723..e4aaa3c 100644
--- a/configs/learning_gem5/part1/caches.py
+++ b/configs/learning_gem5/part1/caches.py
@@ -59,7 +59,7 @@
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
@@ -125,7 +125,7 @@
self.size = opts.l2_size
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
diff --git a/configs/learning_gem5/part1/two_level.py
b/configs/learning_gem5/part1/two_level.py
index 4e7e900..591be0c 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -113,18 +113,18 @@
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
- system.cpu.interrupts[0].pio = system.membus.master
- system.cpu.interrupts[0].int_master = system.membus.slave
- system.cpu.interrupts[0].int_slave = system.membus.master
+ system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+ system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+ system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
# Connect the system up to the membus
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
# Create a DDR3 memory controller
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
-system.mem_ctrl.port = system.membus.master
+system.mem_ctrl.port = system.membus.mem_side_ports
system.workload = SEWorkload.init_compatible(args.binary)
diff --git a/configs/learning_gem5/part2/simple_cache.py
b/configs/learning_gem5/part2/simple_cache.py
index b7465dc..adda386 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -64,22 +64,22 @@
system.cpu.dcache_port = system.cache.cpu_side
# Hook the cache up to the memory bus
-system.cache.mem_side = system.membus.slave
+system.cache.mem_side = system.membus.cpu_side_ports
# create the interrupt controller for the CPU and connect to the membus
system.cpu.createInterruptController()
-system.cpu.interrupts[0].pio = system.membus.master
-system.cpu.interrupts[0].int_master = system.membus.slave
-system.cpu.interrupts[0].int_slave = system.membus.master
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
-system.mem_ctrl.port = system.membus.master
+system.mem_ctrl.port = system.membus.mem_side_ports
# Connect the system up to the membus
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
# Create a process for a simple "Hello World" application
process = Process()
diff --git a/configs/learning_gem5/part2/simple_memobj.py
b/configs/learning_gem5/part2/simple_memobj.py
index f8bafea..49b0846 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -62,22 +62,22 @@
system.membus = SystemXBar()
# Connect the memobj
-system.memobj.mem_side = system.membus.slave
+system.memobj.mem_side = system.membus.cpu_side_ports
# create the interrupt controller for the CPU and connect to the membus
system.cpu.createInterruptController()
-system.cpu.interrupts[0].pio = system.membus.master
-system.cpu.interrupts[0].int_master = system.membus.slave
-system.cpu.interrupts[0].int_slave = system.membus.master
+system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
-system.mem_ctrl.port = system.membus.master
+system.mem_ctrl.port = system.membus.mem_side_ports
# Connect the system up to the membus
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
# Create a process for a simple "Hello World" application
process = Process()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I06ba4a337d947d22c39b5de3ba6700d64bda02c4
Gerrit-Change-Number: 47839
Gerrit-PatchSet: 1
Gerrit-Owner: Melissa Jost <melissakj...@gmail.com>
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